LP8754 datasheet(27/52 Pages) TI2

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R/W

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 7

Bit 6

MSB

LSB

C Slave Address (chip address)

ack from slave

start

MSB Chip Addr LSB

SCL

ack from slave

MSB Register Addr LSB

MSB

Data

LSB

stop

ack from slave

nack from master

repeated start

data from slave

SDA

start

id =60h

w ack

address = 3Fh

ack

r ack

address 3Fh data

nack

stop

MSB Chip Address LSB

id = 60h

start

MSB Chip Addr LSB

ack

MSB Register Addr LSB

ack

MSB

Data LSB

ack

stop

ack from slave

SCL

SDA

start

id = 60h

ack

addr = 40h

ack

address 40h data

stop

LP8754

www.ti.com

SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014

Programming (continued)

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked

out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the

master), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”

indicates a READ. The second byte selects the register to which the data will be written. The third byte contains

data to write to the selected register.

Figure 21. Write Cycle (w = write; SDA = '0'), id = device address = 60Hex for LP8754.

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 22. Read Cycle ( r = read; SDA = '1'), id = device address = 60Hex for LP8754.

7.5.1.4 I2C-Compatible Chip Address

The device address for the LP8754 is 0x60 (ADDR pin tied to the GND). After the START condition, the I2C

master sends the 7-bit address followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and

R/W = 1 indicates a READ. The second byte following the device address selects the register address to which

the data will be written. The third byte contains the data for the selected register.

Here device address is 1100000Bin = 60 Hex.

Figure 23. Device Address

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