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LP8754 Datasheet(PDF) 24 Page - Texas Instruments |
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LP8754 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 52 page ![]() Yes INT Requested If THSD low then enable power outputs TEMP[1:0] = 0b11 Power Outputs Disabled TEMP[1:0] = 0b10 TEMP[1:0] = 0b01 TEMP[1:0] = 0b00 Tj > 85°C Yes INT Requested No Tj < 75°C No Tj > 120°C No Tj > 150°C Tj < 110°C No Tj < 125°C No Read FLAGS_0 INT Released Read FLAGS_0 INT Released Read FLAGS_0 Yes INT Requested T_WARNING Asserted Yes INT Requested THSD Asserted Yes INT Requested Clear THSD E\ZULWLQJ¶0' Read FLAGS_0 INT Released THSD De-asserted Clear T_WARNING E\ZULWLQJ¶0' INT by T_WARNING released Yes INT Requested INT by change in TEMP released No LP8754 SNVS861A – FEBRUARY 2014 – REVISED AUGUST 2014 www.ti.com Note that INT is asserted whenever any of the thermal thresholds is crossed, if unmasked. Note also the 10°C Hysteresis on the TJ Thresholds. Figure 17. Thermal Warnings and Thermal Shutdown Flow 7.4 Device Functional Modes SHUTDOWN: All switch, reference, control and bias circuitry of the LP8754 are turned off. The main battery supply voltage is high enough to start the buck power-up sequence but VVIOSYS and NRST are LOW. STANDBY: Setting VVIOSYS HIGH enables standby-operation. All registers can be read or written by the system master via the system serial interface. Recovery from UVLO, TSD, or OVP event also leads to standby. ACTIVE: Regulated DC/DC converters are on or can be enabled with full current capability. In this mode, all features and control registers are available via the system serial bus and via DVS interface. LOW-POWER: At light loads (less than ~30 mA), and when the load does not require highest level of transient performance, the device enters automatically Low-Power mode. In this mode the part operates at low Iq. Conditions entering and exiting Low-Power mode are shown in Figure 18. 24 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: LP8754 |
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