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DP83849IFVS/NOPB Datasheet(PDF) 6 Page - Texas Instruments |
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DP83849IFVS/NOPB Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 108 page ![]() DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 3 Pin Descriptions The DP83849IF pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • JTAG Interface • Reset and Power Down • Strap Options • 10/100 Mb/s PMD Interface • Special Connect Pins • Power and Ground Pins NOTE Strapping pin option. Please see Section 3.9 for strap definitions. All DP83849IF signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. Type: I Input Type: O Output Type: I/O Input/Output Type OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap value is to be changed then an external 2.2 k Ω resistor should be used. Please see Section 3.9 for details.) 6 Pin Descriptions Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83849IF |
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