DP83849IFVSSLASHNOPB datasheet(10/108 Pages) TI2

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DP83849IF

SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

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Signal Name

Type

Pin #

Description

COL_A

MII COLLISION DETECT: Asserted high to indicate detection of a collision condition

COL_B

(simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a

duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).

In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no

heartbeat function during 10 Mb/s full duplex operation.

RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will

recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine

collision.

SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition

(simultaneous transmit and receive activity) in 10 Mb/s SNI mode.

3.5

CLOCK INTERFACE

Signal Name

Type

Pin #

Description

CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the

DP83849IF and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The

DP83849IF supports either an external crystal resonator connected across pins X1 and X2, or

an external CMOS-level oscillator source connected to pin X1 only.

RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode

and must be connected to a 50 MHz 0.005% (±50 ppm) CMOS-level oscillator source.

CRYSTAL OUTPUT: This pin is the primary clock reference output to connect to an external

25 MHz crystal resonator device. This pin must be left unconnected if an external CMOS

oscillator clock source is used.

CLK2MAC

CLOCK TO MAC:

In MII mode, this pin provides a 25 MHz clock output to the system.

In RMII mode, this pin provides a 50 MHz clock output to the system.

This allows other devices to use the reference clock from the DP83849IF without requiring

additional clock sources.

If the system does not require the CLK2MAC signal, the CLK2MAC output should be disabled

via the CLK2MAC disable strap.

3.6

LED INTERFACE

The DP83849IF supports three configurable LED pins. The LEDs support two operational modes which

are selected by the LED mode strap and a third operational mode which is register configurable. The

definitions for the LEDs for each mode are detailed below. Since the LEDs are also used as strap options,

the polarity of the LED output is dependent on whether the pin is pulled up or down.

Signal Name

Type

Pin #

Description

LED_LINK_A

I/O

LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be

LED_LINK_B

ON when Link is good.

LINK/ACT LED: In Mode 2 and Mode 3, this pin indicates transmit and receive

activity in addition to the status of the Link. The LED will be ON when Link is

good. It will blink when the transmitter or receiver is active.

LED_SPEED_A

I/O

SPEED LED: The LED is ON when device is in 100 Mb/s and OFF when in 10

Mb/s. Functionality of this LED is independent of mode selected.

LED_SPEED_B

LED_ACT/LED_COL_A

I/O

ACTIVITY LED: In Mode 1, this pin is the Activity LED which is ON when activity

LED_ACT/LED_COL_B

is present on either Transmit or Receive.

COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision

detection. For Mode 3, this LED output may be programmed to indicate Full-

duplex status instead of Collision.

Pin Descriptions

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