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DP83849IFVS/NOPB Datasheet(PDF) 89 Page - Texas Instruments |
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DP83849IFVS/NOPB Datasheet(HTML) 89 Page - Texas Instruments |
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89 / 108 page ![]() DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Table 10-21. PHY Control Register (PHYCR), address 19h (continued) Bit Bit Name Default Description 7 BP_STRETCH 0, RW Bypass LED Stretching: This will bypass the LED stretching and the LEDs will reflect the internal value. 1 = Bypass LED stretching. 0 = Normal operation. 6 LED_CNFG[1] 0, RW LED Configuration 5 LED_CNFG[0] Strap, RW LED_CNFG[1] LED_CNFG[0] Mode Description Don't care 1 Mode 1 0 0 Mode 2 1 0 Mode 3 In Mode 1, LEDs are configured as follows: LED_LINK = ON for Good Link, OFF for No Link LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s LED_ACT/LED_COL = ON for Activity, OFF for No Activity In Mode 2, LEDs are configured as follows: LED_LINK = ON for good Link, BLINK for Activity LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s LED_ACT/LED_COL = ON for Collision, OFF for No Collision Full Duplex, OFF for Half Duplex In Mode 3, LEDs are configured as follows: LED_LINK = ON for Good Link, BLINK for Activity LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s LED_ACT/LED_COL = ON for Full Duplex, OFF for Half Duplex 4:0 PHYADDR[4:0] Strap, RW PHY Address: PHY address for port. Copyright © 2009–2013, Texas Instruments Incorporated Register Block 89 Submit Documentation Feedback Product Folder Links: DP83849IF |
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