DP83849IFVSSLASHNOPB datasheet(96/108 Pages) TI2

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DP83849IF

SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

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10.3.7

Variance Control Register (VAR_CTRL), Page 2, address 1Ah

The Variance Control and Data Registers provide control and status for the Cable Signal Quality

Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an

approximate Signal-to-Noise Ratio for the 100Mb receiver. This register contains the programmable

controls and status bits for the variance computation, which can be used to make a simple Signal-to-Noise

Ratio estimation.

Table 10-32. Variance Control Register (VAR_CTRL), address 1Ah

Bit

Bit Name

Default

Description

VAR_RDY

0, RO

Variance Data Ready Status:

Indicates new data is available in the Variance data register. This bit will be

automatically cleared after two consecutive reads ot VAR_DATA.

14:4

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

VAR_FREEZE

0, RW

Freeze Variance Registers:

Freeze VAR_DATA register.

This bit is ensures that VAR_DATA register is frozen for software reads. This bit is

automatically cleared after two consecutive reads of VAR_DATA.

2:1

VAR_TIMER

0, RW

Variance Computation Timer (in ms):

Selects the Variance computation timer period. After a new value is written,

computation is automatically restarted. New variance register values are loaded

after the timer elapses.

Var_Timer = 0 => 2 ms timer (default)

Var_Timer = 1 => 4 ms timer

Var_Timer = 2 => 6 ms timer

Var_Timer = 3 => 8 ms timer

Time units are actually 217 cycles of an 8ns clock, or 1.048576ms.

VAR_ENABLE

0, RW

Variance Enable:

Enable Variance computation. Off by default.

10.3.8

Variance Data Register (VAR_DATA), Page 2, address 1Bh

This register contains the 32-bit Variance Sum. The contents of the data are valid only when VAR_RDY is

asserted in the VAR_CTRL register. Upon detection of VAR_RDY asserted, software should set the

VAR_FREEZE bit in the VAR_CTRL register to prevent loading of a new value into the VAR_DATA

value.

Table 10-33. Variance Data Register (VAR_DATA), address 1Bh

Bit

Bit Name

Default

Description

15:0

VAR_DATA

0, RO

Variance Data:

Two reads are required to return the full 32-bit Variance Sum value. Following

setting the VAR_FREEZE control, the first read of this register will return the low 16

bits of the Variance data. A second read will return the high 16 bits of Variance data.

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