DP83849IFVSSLASHNOPB datasheet(97/108 Pages) TI2

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DP83849IF

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SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

10.3.9

Link Quality Monitor Register (LQMR), Page 2, address 1Dh

This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides

a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an

interrupt will be asserted if enabled in the MISR. Monitor control and status are available in this register,

while the LQDR register controls read/write access to threshold values and current parameter values.

Reading of LQMR register clears warning bits and re-arms the interrupt generation. In addition, this

Monitor status.

Table 10-34. Link Quality Monitor Register (LQMR), address 1Dh

Bit

Bit Name

Default

Description

LQM_ENABLE

0, RW

Link Quality Monitor Enable:

Enables the Link Quality Monitor. The enable is qualified by having a valid 100Mb

link. In addition, the individual thresholds can be disabled by setting to the max or

min values.

14:10

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

FC_HI_WARN

0, RO/COR

Frequency Control High Warning:

This bit indicates the Frequency Control High Threshold was exceeded. This

FC_LO_WARN

0, RO/COR

Frequency Control Low Warning:

This bit indicates the Frequency Control Low Threshold was exceeded. This

FREQ_HI_WARN

0, RO/COR

Frequency Offset High Warning:

This bit indicates the Frequency Offset High Threshold was exceeded. This register

bit will be cleared on read.

FREQ_LO_WARN

0, RO/COR

Frequency Offset Low Warning:

This bit indicates the Frequency Offset Low Threshold was exceeded. This register

bit will be cleared on read.

DBLW_HI_WARN

0, RO/COR

DBLW High Warning:

This bit indicates the DBLW High Threshold was exceeded. This register bit will be

cleared on read.

DBLW_LO_WARN

0, RO/COR

DBLW Low Warning:

This bit indicates the DBLW Low Threshold was exceeded. This register bit will be

cleared on read.

DAGC_HI_WARN

0, RO/COR

DAGC High Warning:

This bit indicates the DAGC High Threshold was exceeded. This register bit will be

cleared on read.

DAGC_LO_WARN

0, RO/COR

DAGC Low Warning:

This bit indicates the DAGC Low Threshold was exceeded. This register bit will be

cleared on read.

C1_HI_WARN

0, RO/COR

C1 High Warning:

This bit indicates the DEQ C1 High Threshold was exceeded. This register bit will

be cleared on read.

C1_LO_WARN

0, RO/COR

C1 Low Warning:

This bit indicates the DEQ C1 Low Threshold was exceeded. This register bit will

be cleared on read.

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