DP83849IFVSSLASHNOPB datasheet(93/108 Pages) TI2

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DP83849IF

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SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

10.3 LINK DIAGNOSTICS REGISTERS - PAGE 2

Page 2 Link Diagnostics Registers are accessible by setting bits [1:0] = 10 of PAGESEL (13h).

10.3.1

100Mb Length Detect Register (LEN100_DET), Page 2, address 14h

This register contains linked cable length estimation in 100Mb operation. The cable length is an estimation

of the effective cable length based on the characteristics of the recovered signal. The cable length is valid

only during 100Mb operation with a valid Link status indication.

Table 10-26. 100Mb Length Detect Register (LEN100_DET), address 14h

Bit

Bit Name

Default

Description

15:8

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

7:0

CABLE_LEN

0, RO

Cable Length Estimate:

Indicates an estimate of effective cable length in meters. A value of FF

indicates cable length cannot be determined.

10.3.2

100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h

This register returns an indication of clock frequency offset relative to the link partner. Two values can be

read, the long term Frequency Offset, or a short term Frequency Control value. The Frequency Control

value includes short term phase correction. The variance between the Frequency Control value and the

Frequency Offset can be used as an indication of the amount of jitter in the system.

Table 10-27. 100Mb Frequency Offset Indication Register (FREQ100), address 15h

Bit

Bit Name

Default

Description

SAMPLE_FREQ

0, RW

Sample Frequency Offset:

If Sel_FC is set to a 0, then setting this bit to a 1 will poll the DSP for

the long-term Frequency Offset value. The value will be available in

the Freq_Offset bits of this register.

If Sel_FC is set to a 1, then setting this bit to a 1 will poll the DSP for

the current Frequency Control value. The value will be available in the

Freq_Offset bits of this register.

This register bit will always read back as 0.

14:9

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

SEL_FC

0, RW

Select Frequency Control:

Setting this bit to a 1 will select the current Frequency Control value

instead of the Frequency Offset. This value contains Frequency Offset

plus the short term phase correction and can be used to indicate

amount of jitter in the system. The value will be available in the

Freq_Offset bits of this register.

7:0

FREQ_OFFSET

0, RO

Frequency Offset:

Frequency offset value loaded from the DSP following assertion of the

Sample_Freq control bit. The Frequency Offset or Frequency Control

value is a twos-complement signed value in units of approximately

5.1562ppm. The range is as follows:

0x7F = +655ppm

0x00 = 0ppm

0x80 = -660ppm

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