DP83849IFVSSLASHNOPB datasheet(85/108 Pages) TI2

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DP83849IF

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SNOSAX8D – JUNE 2009 – REVISED APRIL 2013

10.2.3

100 Mb/s PCS Configuration and Status Register (PCSR)

This register contains control and status information for the 100BASE Physical Coding Sublayer.

Table 10-18. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h

Bit

Bit Name

Default

Description

15:12

RESERVED

<00>, RO

RESERVED: Writes ignored, read as 0.

FREE_CLK

0, RW

Receive Clock:

1 = RX_CLK is free-running.

0 = RX_CLK phase adjusted based on alignment.

TQ_EN

0, RW

100Mbs True Quiet Mode Enable:

1 = Transmit True Quiet Mode.

0 = Normal Transmit Mode.

SD FORCE PMA

0, RW

Signal Detect Force PMA:

1 = Forces Signal Detection in PMA.

0 = Normal SD operation.

SD_OPTION

1, RW

Signal Detect Option:

1 = Default operation. Link will be asserted following detection of valid signal level

and Descrambler Lock. Link will be maintained as long as signal level is valid. A loss

of Descrambler Lock will not cause Link Status to drop.

0 = Modified signal detect algorithm. Link will be asserted following detection of valid

signal level and Descrambler Lock. Link will be maintained as long as signal level is

valid and Descrambler remains locked.

DESC_TIME

0, RW

Descrambler Timeout:

Increase the descrambler timeout. When set this should allow the device to receive

larger packets (>9k bytes) without loss of synchronization.

1 = 2ms.

0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e).

FX_EN

Strap, RW

FX Fiber Mode Enable:

This bit is set when the FX_EN strap option is selected (pulled high) for the

respective port.

1 = Enables FX operation.

0 = Disables FX operation.

FORCE_100_OK

0, RW

Force 100 Mb/s Good Link:

1 = Forces 100 Mb/s Good Link.

0 = Normal 100 Mb/s operation.

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

FEFI_EN

Strap, RW

Far End Fault Indication Mode Enable:

This bit is set when the FX_EN strap option is selected for the respective port.

1 = FEFI Mode Enabled.

0 = FEFI Mode Disabled.

NRZI_BYPASS

0, RW

NRZI Bypass Enable:

1 = NRZI Bypass Enabled.

0 = NRZI Bypass Disabled.

SCRAM

Strap, RW

Scrambler Bypass Enable:

BYPASS

This bit is set when the FX_EN strap option is selected for the respective port. In the

FX mode, the scrambler is bypassed.

1 = Scrambler Bypass Enabled.

0 = Scrambler Bypass Disabled.

DESCRAM

Strap, RW

Descrambler Bypass Enable:

BYPASS

This bit is set when the FX_EN strap option is selected for the respective port. In the

FX mode, the descrambler is bypassed.

1 = Descrambler Bypass Enabled.

0 = Descrambler Bypass Disabled.

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