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OPA320-Q1, OPA2320-Q1

SLOS884B – SEPTEMBER 2014 – REVISED DECEMBER 2018

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Product Folder Links: OPA320-Q1 OPA2320-Q1

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Copyright © 2014–2018, Texas Instruments Incorporated

9 Power Supply Recommendations

The OPAx320-Q1 are specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply

from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or

temperature are presented in the Typical Characteristics section.

CAUTION

Supply voltages larger than 6 V can permanently damage the device (see the Absolute

Maximum Ratings table).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-

impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout

Guidelines section.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational

amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance

power sources local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground

planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically

separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed

information, refer to the Circuit Board Layout Techniques Application Report.

•

To reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace

perpendicular as opposed to in parallel with the noisy trace.

•

Place the external components as close to the device as possible. As shown in Figure 45, keeping RF

and RG close to the inverting input will minimize parasitic capacitance.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.