OPA320SAIDBVT datasheet(8/58 Pages) TI2

8 / 58 page

OPA320, OPA2320, OPA320S, OPA2320S

SBOS513F – AUGUST 2010 – REVISED DECEMBER 2016

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Product Folder Links: OPA320 OPA2320 OPA320S OPA2320S

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Electrical Characteristics (continued)

At VS = 1.8 V to 5.5 V or ±0.9 V to ±2.75 V, TA = 25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, VOUT = VS/2, and

SHDN x = VS+ (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(1)

Based on simulation.

(2)

Third-order filter; bandwidth = 80 kHz at –3 dB.

(3)

Specified by design and characterization; not production tested.

(4)

Disable time (tOFF) and enable time (tON) are defined as the time between the 50% point of the signal applied to the SHDN pin and the

point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

(5)

Full shutdown refers to the dual OPA2320S having both A and B channels disabled (SHDN A = SHDN B = VS–). For partial shutdown,

only one SHDN pin is exercised; in this mode, the internal biasing and oscillator remain operational and the enable time is shorter.

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

2.8

µVPP

Input voltage noise density

f = 1 kHz

8.5

nV/

√Hz

f = 10 kHz

Input current noise density

f = 1 kHz

0.6

fA/

√Hz

INPUT CAPACITANCE

Differential

Common mode

OPEN-LOOP GAIN

AOL

Open-loop voltage gain

0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = 25°C

114

132

0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ, TA = –40°C to 125°C

100

130

0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = 25°C

108

123

0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ, TA = –40°C to 125°C

130

Phase margin

VS = 5 V, CL = 50 pF

FREQUENCY RESPONSE, VS = 5 V, CL = 50 pF

GBP

Gain bandwidth product

Unity gain

MHz

Slew rate

G = +1

V/µs

Settling time

to 0.1%, 2-V step, G = +1

0.25

µs

to 0.01%, 2-V step, G = +1

0.32

to 0.0015%, 2-V step, G = +1(1)

0.5

Overload recovery time

VIN × G > VS

100

THD+N

Total harmonic distortion +

noise(2)

VO = 4 VPP, G = 1, f = 10 kHz, RL = 10 kΩ

0.0005%

VO = 2 VPP, G = 1, f = 10 kHz, RL = 600 Ω

0.0011%

OUTPUT

Voltage output swing from

both rails

RL = 10 kΩ, TA = 25°C

RL = 2 kΩ, TA = 25°C

RL = 10 kΩ, TA = –40°C to 125°C

RL = 2 kΩ, TA = –40°C to 125°C

ISC

Short-circuit current

VS = 5.5 V

±65

Capacitive load drive

See Typical Characteristics

Open-loop output resistance

IO = 0 mA, f = 1 MHz

SHUTDOWN (3)

IQSD

Quiescent current per

amplifier

All amplifiers disabled, SHDN = V–

0.1

0.5

µA

OPA2320S only, SHDN A = VS–, SHDN B = VS+

1.6

OPA2320S only, SHDN A = VS+, SHDN B = VS–

1.6

VIH

High-level input voltage

Amplifier enabled, VS– + 0.7 [(VS+) + |VS–|]

0.7 × VS+

5.5

VIL

Low-level input voltage

Amplifier disabled, VS– + 0.3 [(VS+) + |VS–|]

0.3 × VS+

tON

Amplifier enable time(4)

G = 1, VOUT = 0.1 × VS/2, full shutdown

(5)

µs

OPA2320S only, partial shutdown(5)

tOFF

Amplifier disable time(4)

G = 1, VOUT = 0.1 × VS/2

µs

SHDN pin input bias current

(per pin)

VIH = 5 V

0.13

µA

VIL = 0 V

0.04

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