Pin Functions

PIN

I/O(1)

DESCRIPTION

NAME

NO.

DHL/ZVDL

1

IO

In PWM mode, sets the dead time for high-to-low transition by connecting a resistor to AGND.

In IIM mode, zero-voltage detection output signal to indicate if low-side FET achieves zero-voltage

switching in current switching cycle. Note: Do not Tie ZVDL to GVDD.

DLH/ZVDH

2

IO

In PWM mode, sets the dead time for low-to-high transition by connecting a resistor to AGND.

In IIM mode, zero-voltage detection output signal to indicate if high-side FET achieves zero-voltage

switching in current switching cycle.

RDLR

3

I

Sets the slew-rate control for LS FET turn-on through resistor to AGND.

RDLF

4

I

Sets the slew-rate control for LS FET turn-off through resistor to AGND.

Float this pin to enable PWM mode.

OUT

5

P

Switching node. Internally connected to HS pin.

PGND

6, 17, 18

G

Power ground. Low-side GaN FET source. Internally connected to low-side GaN FET source.

VM

7

P

Input voltage pin. Internally connected to high-side GaN FET drain.

RDHF

8

I

Sets the slew-rate control for HS FET turn-off through resistor to HS.

RDHR

9

I

Sets the slew-rate control for HS FET turn-on through resistor to HS. Note: Do not float RDHR pin.

BOOT

10

P

High-side gate driver bootstrap rail. Connect bypass capacitor to HS.

HS

11

P

High-side GaN FET source connection.

ENIN/HI

12

I

In PWM mode, enables gate-drive for both high-side and low-side FETs.

In IIM mode, high-side gate driver control input.

PWM/LI

13

I

In PWM mode, PWM input.

In IIM mode, low-side gate driver control input.

GVDD

14

P

5V device power supply.

AGND

15

G

Analog ground. Internally connected to low-side GaN FET source.

EN/FLT

16

IO

Chip enable and Fault output pin. Connect to microcontoller output or to GVDD through 4.7 kΩ

resistor.

(1)

I = Input, O = Output, IO = Input/Output, G = Ground, P = Power

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DRV7167

SLVSJF0 – OCTOBER 2025

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