7 Detailed Description

7.1 Overview

Figure 7-1 shows the DRV7167A, half-bridge, GaN power stage with highly integrated high-side and low-side

gate drivers and two GaN FETs in a half-bridge configuration. The device can be used in many isolated and non-

isolated topologies allowing very simple integration. The package is designed to minimize the loop inductance

while keeping the PCB design simple. The drive strengths for turnon and turnoff are optimized to ensure high

voltage slew rates without causing any excessive ringing on the gate or power loop. The device includes several

features to improve system performance and protection.

7.2 Functional Block Diagram

Figure 7-1 shows the functional block diagram of the DRV7167A device with integrated high-side and low-side

GaN FETs.

OUT

PGND

VM

BOOT

GVDD

AGND

Level Shifters

HS

GaN

GaN

RDLR

RDLF

Driver

Driver

RDHR

RDHF

UVLO

and

Control

ENIN/HI

PWM/LI

EN/FLT

DHL/ZVDL

DLH/ZVDH

SYNCBOOT

SCP

ZVD

OTP

SCP

ZVD

UVLO

and

OVR

and

Control

GVDD

OUT

Figure 7-1. Functional Block Diagram

www.ti.com

DRV7167

SLVSJF0 – OCTOBER 2025

Copyright © 2025 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: DRV7167