5.4 Thermal Information_DRV7167A

THERMAL METRIC (1)

DRV7167

UNIT

QFN

18 PINS

R θJA

Junction-to-ambient thermal resistance

27

°C/W

R θJC(top)

Junction-to-case (top) thermal resistance

0.4

°C/W

R θJC(Bot)

Junction-to-case (bottom) thermal resistance, low-side FET to PGND

5.4

°C/W

Junction-to-case (bottom) thermal resistance, high-side FET to VM

6.3

°C/W

R θJB

Junction-to-board thermal resistance

3.9

°C/W

ψ JT

Junction-to-top characterization parameter

1.8

°C/W

ψ JB

Junction-to-board characterization parameter

3.8

°C/W

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .

5.5 Electrical Characteristics

Unless otherwise noted, voltages are with respect to AGND and typical specifications are at 25

℃ (1); -40℃ ≤ TJ ≤150℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER STAGE_DRV7167A

RDS(ON)HS

High-side GaN FET on-resistance

LI=0V, HI=GVDD=5V, BOOT-HS=5V,

I(VM-OUT)=16A, TJ = 25℃

2.3

3.1

mΩ

RDS(ON)LS

Low-side GaN FET on-resistance

LI=GVDD=5V, HI=0V, BOOT-HS=5V,

I(OUT-PGND)=16A, TJ = 25℃

2.2

3

mΩ

VSD

GaN source to drain 3rd quadrant

conduction drop

ISD = 500 mA, VM floating, VGVDD = 5 V, HI

= LI = 0V

1.5

V

IL-VM-OUT

Leakage from VM to OUT when the high-

side GaN FET and low-side GaN FET are

off

VM = 80V, OUT=0V, HI = LI = 0V, VGVDD =

5V, TJ=25℃

10

150

µA

IL-VM-OUT

Leakage from VM to OUT when the high-

side GaN FET and low-side GaN FET are

off

VM = 80V, OUT=0V, HI = LI = 0V, VGVDD =

5V, TJ=90℃

20

300

µA

IL-OUT-GND

Leakage from OUT to GND when the

high-side GaN FET and low-side GaN

FET are off

OUT = 80V, HI = LI = 0V, VGVDD =

5V, TJ=25℃

10

150

µA

IL-OUT-GND

Leakage from OUT to GND when the

high-side GaN FET and low-side GaN

FET are off

OUT = 80V, HI = LI = 0V, VGVDD =

5V, TJ=90℃

20

300

µA

CISS

Input Capacitance of high side or low side

HEMT

VDS=50V, VGS= 0V (HI = LI =

0V), TJ=25℃

1700

pF

COSS

Output Capacitance of high-side GaN FET

or low-side GaN FET

VDS=50V, VGS= 0V (HI = LI =

0V), TJ=25℃

570

pF

COSS(ER)

Output Capacitance of high-side GaN FET

or low-side GaN FET - Energy Related

VDS=0 to 50V, VGS= 0V (HI = LI =

0V), TJ=25℃

700

pF

COSS(TR)

Output Capacitance of high-side GaN FET

or low-side GaN FET - Time Related

VDS=0 to 50V, VGS= 0V (HI = LI =

0V), TJ=25℃

880

pF

CRSS

Reverse Transfer Capacitance of high

side or low side HEMT

VDS=50V, VGS= 0V (HI = LI =

0V), TJ=25℃

4.3

pF

QG

Total Gate Charge of high side or low side

HEMT

VDS=50V, ID= 16A, VGS= 5V, TJ=25℃

12

nC

QGD

Gate to Drain Charge of high side or low

side HEMT

VDS=50V, ID= 16A, TJ=25℃

1.2

nC

QGS

Gate to Source Charge of high side or low

side HEMT

VDS=50V, ID= 16A, TJ=25℃

3.9

nC

QOSS

Output Charge (sum of high side HEMT,

low side HEMT and gate-driver HV-Well

charge)

VDS=50V, ID= 16A, TJ=25℃

90

nC

QRR

Source to Drain Reverse Recovery

Charge

0

nC

tHIPLH

Propagation delay: HI Rising(2)

LI=0V, GVDD=5V, BOOT-HS=5V,

VM=48V

15

25

ns

DRV7167

SLVSJF0 – OCTOBER 2025

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