Unless otherwise noted, voltages are with respect to AGND and typical specifications are at 25

℃ (1); -40℃ ≤ TJ ≤150℃

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Rgrh

RDHR = 0 Ω

Voltage across driver FET = 1.2V

0.8

Ω

RDHR = 4 kΩ

3.6

RDHR = 8 kΩ

7

RDHR =16 kΩ

14

Rgrl

RDLR = 0 Ω

Voltage across driver FET = 1.2V

0.8

Ω

RDLR = 4 kΩ

3.6

RDLR = 8 kΩ

7

RDLR =16 kΩ

14

DEAD TIME CONTROL

tDEAD_MIN

Minimum Dead Time

DLH, DHL = 0Ω; Minimum Dead time

setting.

5

7.5

10

ns

tDEAD_MAX

Maximum Dead Time

DLH, DHL = 100kΩ; Maximum Dead time

setting.

32

40

48

ns

OCP

VDSAT

Saturation protection voltage threshold

0.75

V

tBLANK

Blanking time for VDSAT detection

38

60

88

ns

tSATFLT

Time to indicate FLT upon VDS

overvoltage detection after blanking time

28.7

ns

ZVD Output (Active Low)

VTHRESH_ZVD ZVD Detector Threshold

0.8

1.0

V

t3RD_ZVD

Minimum third quadrant time that can be

detected by ZVD detector (Low Side)

For a 0 to -1.5V to 0 pulse with 100ps rise/

fall time

6

10

14

ns

t3RD_ZVD

Minimum third quadrant time that can be

detected by ZVD detector (High Side)

For a 0 to -1.5V to 0 pulse with 100ps rise/

fall time

6

10

14

ns

tDLY_ZVD_L

Delay between VTHRESH_ZVD cross vs ZVD

output going low

For a 0 to -1.5V to 0 pulse with 100ps rise/

fall time

20

30

ns

tDLY_ZVD_H

Delay between VTHRESH_ZVD cross vs ZVD

output going low

For a 0 to -1.5V to 0 pulse with 100ps rise/

fall time

20

30

ns

tWD_ZVD

ZVD pulse width

For a 0 to -1.5V to 0 pulse with 100ps rise/

fall time

40

65

95

ns

OTD

OTD+

Over Temperature Detect high threshold

145

165

182

℃

OTD-

Over Temperature Detect high threshold

135

154

170

℃

OTDHYS

Over Temperature Detect high threshold

12

℃

FAULT

IFLT

Fault pin pull down current

VFLT = 0.4 V

3

mA

tFLTDLY

Time to indicate FLT after fault occurs

20

ns

tFLT

Min fault indication time

10

µs

tENBLK

Time after FLT release, after which EN=0

is effective

1

µs

(1)

Parameters that show only a typical value are determined by design and may not be tested in production

(2)

See Propagation Delay and Mismatch Measurement section

DRV7167

SLVSJF0 – OCTOBER 2025

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