BCK

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

DATA

LRCK

DGND

NC

VCC

VOUTL

VOUTR

SCK

AGND

FMT

MUTE

DEMP

TEST

VCOM

ZEROA

10 µF

Post LPF

10 µF

PCM1754

+5 V

+

L-Ch Out

PCM Audio Data

Post LPF

R-Ch Out

System Clock

Zero Mute Control

Format

MUTE On/Off

DEMP On/Off

10 µF

10 µF

24

PCM1753, PCM1754, PCM1755

SLES092E – APRIL 2003 – REVISED JULY 2019

www.ti.com

Product Folder Links: PCM1753 PCM1754 PCM1755

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Copyright © 2003–2019, Texas Instruments Incorporated

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The delta-sigma section of the PCM175x device is based on an 8-level amplitude quantizer and a 4th-order noise

shaper. This section converts the oversampled input data to 8-level delta-sigma format. A block diagram of the 8-

level delta-sigma modulator is shown in Figure 32. This 8-level delta-sigma modulator has the advantage of

stability and clock jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator.

The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64 fS.

The theoretical quantization noise performance of the 8-level delta-sigma modulator is shown in Figure 35 and

Figure 36. The enhanced multilevel delta-sigma architecture also has advantages for input clock jitter sensitivity

due to the multilevel quantizer, with the simulated jitter sensitivity shown in Figure 37.

The PCM175X devices are suitable for a wide variety of cost-sensitive consumer applications requiring good

performance and operation with a single 5-V supply.

9.2 Typical Application

A basic connection diagram is shown in Figure 30, with the necessary power supply bypassing and decoupling

components. TI recommends using the component values shown in Figure 30 for all designs.

The use of series resistors (22 Ω to 100 Ω) is recommended for the SCK, LRCK, BCK, and DATA inputs. The

series resistor combines with the stray PCB and device input capacitance to form a low-pass filter, which reduces

high-frequency noise emissions and helps to dampen glitches and ringing present on clock and data lines.

For this design example, use the parameters listed in Table 7.

Figure 30. Basic Connection Diagram