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PCM1753, PCM1754, PCM1755

SLES092E – APRIL 2003 – REVISED JULY 2019

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Product Folder Links: PCM1753 PCM1754 PCM1755

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Copyright © 2003–2019, Texas Instruments Incorporated

Electrical Characteristics (continued)

all specifications at TA = 25°C, VCC = 5 V, fS = 44.1 kHz, system clock = 384 fS, and 24-bit data (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG OUTPUT

Output voltage

Full scale (0 dB)

80% of

VCC

VPP

Center voltage

50% of

VCC

VDC

Load impedance

AC-coupled load

5

kΩ

DIGITAL FILTER PERFORMANCE

FILTER CHARACTERISTICS (SHARP ROLLOFF)

Pass band

±0.04 dB

0.454 fS

Stop band

0.546 fs

Pass-band ripple

±0.04

dB

Stop-band attenuation

Stop band = 0.546 fS

–50

dB

ANALOG FILTER PERFORMANCE

Frequency response

At 20 kHz

–0.03

dB

At 44 kHz

–0.2

POWER SUPPLY REQUIREMENTS(2)

ICC

Supply current

fS = 44.1 kHz

16

21

mA

fS = 96 kHz

25

fS = 192 kHz

30

Power dissipation

fS = 44.1 kHz

80

105

mW

fS = 96 kHz

125

fS = 192 kHz

150

TEMPERATURE

RθJA

Thermal Resistance

16-pin DBQ

104.1

°C/W

(1)

1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS.

7.6 System Clock Input Timing

for more information, see the System Clock Input section

MIN

NOM

MAX

UNIT

t(SCKH)

System clock pulse duration, high

See Figure 20.

7

ns

t(SCKL)

System clock pulse duration, low

7

ns

t(SCY)

System clock pulse cycle time

See (1)

ns

(1)

fS is the sampling frequency (for example, 44.1 kHz, 48 kHz, 96 kHz, and so on).

7.7 Audio Interface Timing

for more information, see the Audio Data Formats and Timing section

MIN

MAX

UNIT

t(BCY)

BCK pulse cycle time

See Figure 22.

1/(32 fS)

1/(48 fS)

1/(64 fS)

(1)

t(BCH)

BCK high–level time

35

ns

t(BCL)

BCK low–level time

35

ns

t(BL)

BCK rising edge to LRCK edge

10

ns

t(LB)

LRCK falling edge to BCK rising

edge

10

ns

t(DS)

DATA setup time

10

ns

t(DH)

DATA hold time

10

ns