PCM1840 datasheet(28/41 Pages) TI2

28 / 41 page

PCM1840

SBAS989 – APRIL 2019

www.ti.com

Product Folder Links: PCM1840

Submit Documentation Feedback

Typical Application (continued)

8.2.1 Design Requirements

Table 21 lists the design parameters for this application.

Table 21. Design Parameters

KEY PARAMETER

SPECIFICATION: 3.3-V AVDD OPERATION

AVDD

3.3 V

AVDD supply current consumption

> 23 mA (PLL on, four-channel recording, fS = 48 kHz)

IOVDD

1.8 V or 3.3 V

Maximum MICBIAS current

10 mA (MICBIAS voltage is the same as VREF)

8.2.2 Detailed Design Procedure

This section describes the necessary steps to configure the PCM1840 for this specific application. The following

steps provide a sequence of items that must be executed in the time between powering the device up and

reading data from the device or transitioning from one mode to another mode of operation.

1. Apply power to the device:

a. Power-up the IOVDD and AVDD power supplies, keeping the SHDNZ pin voltage low

b. The device now goes into hardware shutdown mode (ultra-low-power mode < 1 µA)

2. Transition from hardware shutdown mode to active mode whenever required for the recording operation:

a. Connect the MSZ, FMT0, and FMT1 pins voltage low to configure the device in 4-channel TDM slave

mode

b. Release SHDNZ only when the IOVDD and AVDD power supplies settle to the steady-state operating

voltage

c. Apply FSYNC and BCLK with the desired output sample rates and the BCLK to FSYNC ratio

This specific step can be done at any point in the sequence after step a

See the Phase-Locked Loop (PLL) and Clock Generation section for supported sample rates and the

BCLK to FSYNC ratio

d. The device recording data are now sent to the host processor via the TDM audio serial data bus

3. Assert the SHDNZ pin low to enter hardware shutdown mode (again) at any time

4. Follow step 2 onwards to exit hardware shutdown mode (again)

PCM1840 Datasheet(PDF) 28 Page - Texas Instruments