DRE

Amplifier

ADC

Channel-1

Digital Filters

(Linear-Phase and

Low-Latency LPF)

and

Dynamic Range

Enhancer (DRE)

Audio Serial

Interface (TDM,

I

2S, LJ)

Audio Clock

Generation

PLL

(Input Clock

Source - BCLK,

MD1)

Hardware Pin Control

Interface

BCLK

FSYNC

SDOUT

IN1M

IN1P

IN2M

IN2P

IN3M

IN3P

IN4M

IN4P

DRE

Amplifier

ADC

Channel-2

DRE

Amplifier

ADC

Channel-3

DRE

Amplifier

ADC

Channel-4

Microphone

Bias

MICBIAS

SHDNZ

Regulators, Current Bias and

Voltage Reference

10

PCM1840

SBAS989 – APRIL 2019

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Product Folder Links: PCM1840

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Copyright © 2019, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The PCM1840 is a high-performance, low-power, quad-channel, audio analog-to-digital converter (ADC) with

flexible audio interface control options. This device is intended for applications in voice-activated systems, AV

receivers, TV and blu-ray players, professional microphones, audio conferencing, portable computing,

communication, and entertainment applications. The high dynamic range of the device enables far-field audio

recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power

consumption in space-constrained, battery-powered, consumer, home, and industrial applications. The device

features are controlled through hardware by pulling pins high or low with resistors or a controller GPIO. The

PCM1808 also supports a power-down and reset function by means of halting the system clock.

The PCM1840 consists of the following blocks and features:

•

Quad-channel, multibit, high-performance delta-sigma (ΔΣ) ADC

•

Differential audio inputs with a 2-VRMS full-scale signal

•

Low-noise, 1.6-µVRMS, microphone bias output

•

Hardware pin control operation to select the device features

•

Audio bus serial interface master or slave select option

•

Audio bus serial interface format select option

•

Audio bus serial interface supported up to 192 kHz sampling

•

Slave mode supports dynamic range enhancer (DRE) with 123-dB dynamic range

•

Slave mode supports decimation filters with linear-phase or low-latency filter selection

•

Master mode operation supported using system clock of 256 × fS or 512 × fS

•

Power-down function by means of halting the audio clocks

•

Integrated high-pass filter (HPF) that removes the dc component of the input signal

•

Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks

•

Integrated digital and analog voltage regulators to support single-supply 3.3-V operation

7.2 Functional Block Diagram