2

1

0

N-1

N-2

N-3

1

0

Ch1

(Word Length : 32)

Ch2

(Word Length : 32)

FSYNC

BCLK

SDOUT

n

th Sample (64 BCLK Cycles)

(n+1)

th Sample (64 BCLK Cycles)

0

2

1

0

N-1

N-2

N-3

1

N-1

0

Ch1

(Word Length : 32)

Ch2

(Word Length : 32)

N-1

N-2

N-3

N-1

N-2

N-3

2

1

0

N-1

N-2

N-3

2

1

0

N-1

N-2

N-3

1

0

Ch1

(Word Length : 32)

Ch2

(Word Length : 32)

Ch3 to Ch4

(Word Length : 32)

2

1

0

Ch1

(Word Length : 32)

FSYNC

BCLK

SDOUT

n

th Sample ( 128 BCLK Cycles)

(n+1)

th Sample

0

N-1

N-2

N-3

N-1

N-2

N-3

2

1

0

N-1

N-2

N-1

N-2

N-3

2

1

0

Ch1

(Word Length : 32)

Ch2

(Word Length : 32)

2

1

0

N-1

N-2

Ch1

(Word Length : 32)

BCLK

SDOUT

n

th Sample

(n+1)

th Sample

FSYNC

12

PCM1840

SBAS989 – APRIL 2019

www.ti.com

Product Folder Links: PCM1840

Submit Documentation Feedback

Copyright © 2019, Texas Instruments Incorporated

Figure 15. TDM Mode Protocol Timing (FMT0 = HIGH) In Slave Mode

Figure 16. TDM Mode Protocol Timing (FMT0 = LOW) In Master Mode

Figure 17. TDM Mode Protocol Timing (FMT0 = HIGH) In Master Mode

For proper operation of the audio bus in TDM mode, the number of bit clocks per frame must be greater than or

equal to the number of active output channels times the 32-bits word length of the output channel data. The

device transmits a zero data value on SDOUT for the extra unused bit clock cycles. The device supports FSYNC

as a pulse with a 1-cycle-wide bit clock, but also supports multiples as well.

7.3.2.2 Inter IC Sound (I2S) Interface

The standard I2S protocol is defined for only two channels: left and right. In I2S mode, the MSB of the left slot 0 is

transmitted on the falling edge of BCLK in the second cycle after the falling edge of FSYNC. The MSB of the

right slot 0 is transmitted on the falling edge of BCLK in the second cycle after the rising edge of FSYNC. Each

subsequent data bit is transmitted on the falling edge of BCLK. In master mode, FSYNC is transmitted on the

rising edge of BCLK. Figure 18 and Figure 19 illustrate the protocol timing for I2S operation in slave and master

mode of operation.