FSYNC

BCLK

tH(BCLK)

tL(BCLK)

tr(BCLK)

tf(BCLK)

tSU(FSYNC)

tHLD(FSYNC)

td(SDOUT-FSYNC)

td(SDOUT-BCLK)

SDOUT

t(BCLK)

td(FSYNC)

7

PCM1840

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SBAS989 – APRIL 2019

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(1)

The BCLK minimum high or low pulse duration must be higher than 25 ns (to meet the timing specifications), if the SDOUT data line is

latched on the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

6.6 Timing Requirements: TDM, I

2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram

MIN

NOM

MAX

UNIT

t(BCLK)

BCLK period

40

ns

tH(BCLK)

BCLK high pulse duration (1)

18

ns

tL(BCLK)

BCLK low pulse duration (1)

18

ns

tSU(FSYNC)

FSYNC setup time

8

ns

tHLD(FSYNC)

FSYNC hold time

8

ns

tr(BCLK)

BCLK rise time

10% - 90% rise time

10

ns

tf(BCLK)

BCLK fall time

90% - 10% fall time

10

ns

(1)

The BCLK output clock frequency must be lower than 18.5 MHz (to meet the timing specifications), if the SDOUT data line is latched on

the opposite BCLK edge polarity than the edge used by the device to transmit SDOUT data.

6.7 Switching Characteristics: TDM, I

2S or LJ Interface

at TA = 25°C, IOVDD = 3.3 V or 1.8 V and 20-pF load on all outputs (unless otherwise noted); see Figure 3 for timing diagram

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(SDOUT-BCLK)

BCLK to SDOUT delay

50% of BCLK to 50% of SDOUT

18

ns

td(SDOUT-FSYNC)

FSYNC to SDOUT delay in TDM

or LJ mode (for MSB data with

TX_OFFSET = 0)

50% of FSYNC to 50% of

SDOUT

18

ns

f(BCLK)

BCLK output clock frequency:

master mode (1)

24.576

MHz

tH(BCLK)

BCLK high pulse duration:

master mode

14

ns

tL(BCLK)

BCLK low pulse duration: master

mode

14

ns

td(FSYNC)

BCLK to FSYNC delay: master

mode

50% of BCLK to 50% of FSYNC

18

ns

tr(BCLK)

BCLK rise time: master mode

10% - 90% rise time

8

ns

tf(BCLK)

BCLK fall time: master mode

90% - 10% fall time

8

ns

Figure 1. TDM, I2S, and LJ Interface Timing Diagram