2

1

0

N-1

N-2

N-1

N-2

N-3

2

1

0

N-1

N-2

N-3

2

1

0

Ch1

(Word Length : 32)

Ch2

(Word Length : 32)

Ch3 to Ch4

(Word Length : 32)

2

1

0

N-1

N-2

Ch1

(Word Length : 32)

FSYNC

BCLK

SDOUT

n

th Sample

(n+1)

th Sample

11

PCM1840

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SBAS989 – APRIL 2019

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7.3 Feature Description

7.3.1 Hardware Control

The device supports simple hardware pin controlled options to select specific mode of operation and audio

interface for a given system. The MSZ, MD0, MD1, FMT0, and FMT1 pins allow the device to be controlled by

either pullup or pulldown resistors as well as the GPIO from a digital device.

7.3.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the PCM1840 on the digital audio serial interface (ASI),

or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for I2S or left-

justified protocols format, and the pin-selectable master-slave configurability for bus clock lines.

The device supports audio bus master or slave mode of operation using the hardware pin MSZ. In slave mode,

FSYNC and BCLK work as input pins whereas in master mode, FSYNC and BCLK work as output pins

generated by the device.Table 1 shows the master and slave mode selection using the MSZ pin.

Table 1. Master and Slave Mode Selection

MSZ

MASTER AND SLAVE SELECTION

LOW

Slave mode of operation

HIGH

Master ode of operation

The bus protocol TDM, I2S, or left-justified (LJ) format can be selected by using the FMT0 and FMT1 pins. As

shown in Table 2, these modes are all most significant byte (MSB)-first, pulse code modulation (PCM) data

format, with the output channel data word-length of 32 bits.

Table 2. Audio Serial Interface Format

FMT1

FMT0

AUDIO SERIAL INTERFACE FORMAT

LOW

LOW

4-channel output with time division multiplexing (TDM) mode

LOW

HIGH

2-channel output with time division multiplexing (TDM) mode

HIGH

LOW

2-channel output with left-justified (LJ) mode

HIGH

HIGH

2-channel output with inter IC sound (I2S) mode

7.3.2.1 Time Division Multiplexed Audio (TDM) Interface

In TDM mode, also known as DSP mode, the rising edge of FSYNC starts the data transfer with the slot 0 data

first. Immediately after the slot 0 data transmission, the remaining slot data are transmitted in order. FSYNC and

each data bit (except the MSB of slot 0 when TX_OFFSET equals 0) is transmitted on the rising edge of BCLK.

Figure 14 to Figure 17 illustrate the protocol timing for TDM operation with various configurations.

Figure 14. TDM Mode Protocol Timing (FMT0 = LOW) In Slave Mode