6

PCM1840

SBAS989 – APRIL 2019

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Copyright © 2019, Texas Instruments Incorporated

Electrical Characteristics (continued)

at TA = 25°C, AVDD = 3.3 V, IOVDD = 3.3 V, fIN = 1-kHz sinusoidal signal, fS = 48 kHz, 32-bit audio data, BCLK = 256 × fS,

TDM slave mode (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MICROPHONE BIAS

MICBIAS noise

BW = 20 Hz to 20 kHz, A-weighted, 1-μF capacitor

between MICBIAS and AVSS

1.6

µVRMS

MICBIAS voltage

VREF

V

MICBIAS current drive

20

mA

MICBIAS load regulation

Measured up to max load

0.1

0.6

1.8

%

MICBIAS over current

protection threshold

30

mA

DIGITAL I/O

VIL

Low-level digital input logic

voltage threshold

All digital pins, IOVDD 1.8-V operation

–0.3

0.30 ×

IOVDD

V

All digital pins, IOVDD 3.3-V operation

–0.3

0.8

VIH

High-level digital input logic

voltage threshold

All digital pins, IOVDD 1.8-V operation

0.7 ×

IOVDD

IOVDD +

0.3

V

All digital pins, IOVDD 3.3-V operation

2.1

IOVDD +

0.3

VOL

Low-level digital output

voltage

All digital pins, IOL = –2 mA, IOVDD 1.8-V operation

0.45

V

All digital pins, IOL = –2 mA, IOVDD 3.3-V operation

0.4

VOH

High-level digital output

voltage

All digital pins, IOH = 2 mA, IOVDD 1.8-V operation

IOVDD –

0.45

V

All digital pins, IOH = 2 mA, IOVDD 3.3-V operation

2.4

IIH

Input logic-high leakage for

digital inputs

All digital pins, input = IOVDD

–5

0.1

5

µA

IIL

Input logic-low leakage for

digital inputs

All digital pins, input = 0 V

–5

0.1

5

µA

CIN

Input capacitance for

digital inputs

All digital pins

5

pF

RPD

Pulldown resistance for

digital I/O pins when

asserted on

20

kΩ

TYPICAL SUPPLY CURRENT CONSUMPTION

IAVDD

Current consumption in

hardware shutdown mode

SHDNZ = 0, AVDD = 3.3 V, internal AREG

0.5

µA

IIOVDD

SHDNZ = 0, all external clocks stopped, IOVDD = 3.3 V

0.1

IIOVDD

SHDNZ = 0, all external clocks stopped, IOVDD = 1.8 V

0.1

IAVDD

Current consumption with

ADC 4-channel operating

at fS 16-kHz, BCLK = 256

× fS and DRE disable

AVDD = 3.3 V, internal AREG

20.6

mA

IIOVDD

IOVDD = 3.3 V

0.05

IIOVDD

IOVDD = 1.8 V

0.02

IAVDD

Current consumption with

ADC 4-channel operating

at fS 48-kHz, BCLK = 256

× fS and DRE disable

AVDD = 3.3 V, internal AREG

22.3

mA

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05

IAVDD

Current consumption with

ADC 4-channel operating

at fS 48-kHz, BCLK = 256

× fS and DRE enable

AVDD = 3.3 V, internal AREG

24.4

mA

IIOVDD

IOVDD = 3.3 V

0.1

IIOVDD

IOVDD = 1.8 V

0.05