Table 6-10. EQ Gain Control Register (Channel Register Base + Offset = 0x01) (continued)

Bit

Field

Type

Reset

Description

6

eq_stage1_3

R/W

0x0

EQBoost stage 1 control

See Table 6-1 in the data sheet for details

5

eq_stage1_2

R/W

0x0

4

eq_stage1_1

R/W

0x0

3

eq_stage1_0

R/W

0x0

2

eq_stage2_2

R/W

0x0

EQ Boost stage 2 control

See Table 6-1 in the data sheet for details

1

eq_stage2_1

R/W

0x0

0

eq_stage2_0

R/W

0x0

Table 6-11. EQ Gain, Flat Gain Control Register (Channel Register Base + Offset = 0x03)

Bit

Field

Type

Reset

Description

7

RESERVED

R

0x0

Reserved

6

eq_profile_3

R/W

0x0

EQ mid-frequency boost profile

See Table 6-1 in the data sheet for details

5

eq_profile_2

R/W

0x0

4

eq_profile_1

R/W

0x0

3

eq_profile_0

R/W

0x0

2

flat_gain_2

R/W

0x1

Flat gain select:

See Table 6-2 in the data sheet for details

1

flat_gain_1

R/W

0x0

0

flat_gain_0

R/W

0x1

Table 6-12. TI Test Mode Control Register (Channel Register Base + Offset = 0x04)

Bit

Field

Type

Reset

Description

7-3, 1-0

RESERVED

R

0x0

Reserved

2

TI test mode

R/W

0x0

Set TI test mode:

0: test mode is enabled

1: test mode is disabled. Must be set to "1" for normal operation.

Table 6-13. PD Override Register (Channel Register Base + Offset = 0x05)

Bit

Field

Type

Reset

Description

7

device_en_override

R/W

0x0

Enable power down overrides through SMBus/I2C

0: Manual override disabled

1: Manual override enabled

6-0

device_en

R/W

0x111111

Manual power down of redriver various blocks of a channel –

gated by device_en_override = 1

111111: All blocks in the channel are enabled

000000: All blocks in the channel are disabled

Table 6-14. Bias Register (Channel Register Base + Offset = 0x06)

Bit

Field

Type

Reset

Description

5-3

Bias current

R/W

0x100

Control bias current

Set 001 for best performance

7,6,2-0

Reserved

R/W

0x00000

Reserved

6.5.3 SMBus/I2C Controller Mode Configuration (EEPROM Self Load)

The TDP2004-Q1 can also be configured by reading from EEPROM. To enter into this mode MODE pin must

be set to L1. The EEPROM load operation only happens once after the initial powerup of the device. If the

TDP2004-Q1 is configured for SMBus Controller mode, the device remains in the SMBus IDLE state until the

READ_ENn pin is asserted to LOW. After the READ_ENn pin is driven LOW, theTDP2004-Q1 becomes an

SMBus Controller and attempts to self-configure by reading the device settings stored in an external EEPROM

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TDP2004-Q1

SNLS787 – SEPTEMBER 2025

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