TDP2004 datasheet(4/34 Pages) TI2

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Table 4-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

NO.

GND

3, 10, 13, 20,

23, 30, 33, 40,

Ground reference for the device.

EP: the Exposed Pad at the bottom of the QFN package, which is used as the GND

return for the device. The EP must be connected to one or more ground planes

through the low resistance path. A via array provides a low impedance path to GND.

The EP also improves thermal dissipation.

I, 3.3V

LVCMOS

2-level logic controlling the operating state of the redriver. Active in all device control

modes. The pin has internal 1MΩ weak pull down resistor.

High: power down for channels 0-3

Low: power up, normal operation for channels 0-3

READ_ENn

I, 3.3V

LVCMOS

In SMBus/I2C Controller mode:

After power up, when the pin is low, the device initiates the SMBus / I2C Controller

mode EEPROM read function. When EEPROM read is complete (indicated by

assertion of Don En low), this pin can be held low for normal device operation. During

the EEPROM load process the signal path of the device is disabled.

In SMBus/I2C Target and Pin modes:

In these modes the pin is not used. The pin can be left floating. The pin has internal

1MΩ weak pull down resistor.

SEL

The pin selects the mux configuration.

Low: straight data path – RX[0/1/2/3][P/N] connected to TX[0/1/2/3][P/N] through the

redriver.

High: cross data path – RX[0/1/2/3][P/N] connected to TX[1/0/3/2][P/N] through the

redriver.

Active in all device control modes. 59kΩ internal pull down.

TEST / SCL

I, 5-level / I/O,

3.3V

LVCMOS,

open drain

In Pin mode:

TI test mode. External 1kΩ pull down resistor must be installed.

In SMBus/I2C mode:

3.3V SMBus/I2C clock. External 1kΩ to 5kΩ pullup resistor is required as per SMBus /

I2C interface standard.

RX0N

Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from

the pin to internal CM bias voltage. Channel 0.

RX0P

Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor

from the pin to internal CM bias voltage. Channel 0.

RX1N

Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from

the pin to internal CM bias voltage. Channel 1.

RX1P

Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor

from the pin to internal CM bias voltage. Channel 1.

RX2N

Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from

the pin to internal CM bias voltage. Channel 2.

RX2P

Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor

from the pin to internal CM bias voltage. Channel 2.

RX3N

Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from

the pin to internal CM bias voltage. Channel 3.

RX3P

Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor

from the pin to internal CM bias voltage. Channel 3.

TX0N

Inverting pin for 100Ω differential driver output. Channel 0.

TX0P

Non-inverting pin for 100Ω differential driver output. Channel 0.

TX1N

Inverting pin for 100Ω differential driver output. Channel 1.

TX1P

Non-inverting pin for 100Ω differential driver output. Channel 1.

TX2N

Inverting pin for 100Ω differential driver output. Channel 2.

TX2P

Non-inverting pin for 100Ω differential driver output. Channel 2.

TX3N

Inverting pin for 100Ω differential driver output. Channel 3.

TX3P

Non-inverting pin for 100Ω differential driver output. Channel 3.

TDP2004-Q1

SNLS787 – SEPTEMBER 2025

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