Product Specification

LC320DXN

Ver. 1.0

10 / 36

3-3. Signal Timing Specifications

Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal

timings should be satisfied with the following specification for normal operation.

Note: 1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).

If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.

2. The performance of the electro-optical characteristics may be influenced by variance of the vertical

refresh rate and the horizontal frequency

※ Timing should be set based on clock frequency.

Table 6-1. TIMING TABLE (DE Only Mode)

ITEM

Symbol

Min

Typ

Max

Unit

Note

Horizontal

Display

Period

tHV

-

1366

-

tclk

Blank

tHB

90

162

410

tclk

Total

tHP

1456

1528

1776

tclk

Vertical

Display

Period

tVV

-

768

-

tHP

Blank

tVB

20

(126)

22

(180)

240

(295)

tHP

1

Total

tVP

788

(894)

790

(948)

1008

(1063)

tHP

ITEM

Symbol

Min

Typ

Max

Unit

Note

Frequency

DCLK

fCLK

63.0

72.4

80.0

MHz

Horizontal

fH

45

47.4

55

KHz

2

Vertical

fV

57

(47)

60

(50)

63

(53)

Hz

2

NTSC :

57~63Hz

(PAL : 47~53Hz)