LC320DXN datasheet(12/36 Pages) LG

12 / 36 page

Product Specification

LC320DXN

Ver. 1.0

12 / 36

1) DC Specification

2) AC Specification

Description

Symbol

Min

Max

Unit

Note

LVDS Common mode Voltage

VCM

1.0

1.5

LVDS Input Voltage Range

VIN

0.7

1.8

Change in common mode Voltage

ΔVCM

250

LVDS 1’st Clock

clk

LVDS 2nd / 3rd / 4th Clock

SKEW_min tSKEW_max

20%

80%

LVDS Data

tSKEW

LVDS Clock

Tclk

( Fclk = 1 /Tclk )

tSKEW

1. All Input levels of LVDS signals are based on the EIA 644 Standard.

2. If

tRF isn’t enough, teff should be meet the range.

3. LVDS Differential Voltage is defined within

teff

Description

Symbol

Min

Max

Unit

Note

LVDS Differential Voltage

VTH

100

300

VTL

-300

-100

LVDS Clock to Data Skew

tSKEW

|(0.20*Tclk)/7|

LVDS Clock/DATA Rising/Falling time

tRF

260

|(0.3*Tclk)/7|

Effective time of LVDS

teff

|± 360|

LVDS Clock to Clock Skew (Even to Odd)

tSKEW_EO

|1/7* Tclk|

LVDS

# V CM = {( LVDS +) + ( LVDS - )} /2

IN _ MAX

IN _ MIN

High Threshold

Low Threshold

Note

3-4-2. LVDS Input Signal Characteristics

LC320DXN Datasheet(PDF) 12 Page - LG Semicon Co.,Ltd.

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