LM5145 datasheet(60/74 Pages) TI2

60 / 74 page

• Create an analog ground plane near the IC for sensitive analog components. Connect the AGND plane and

the PGND power ground planes at a single point at the die attach pad (DAP) of the IC.

• Increase the width of the BIAS1/VOUT1 trace to minimize the voltage offset related to VCC bias current, as

shown in Figure 8-33.

Place four paralleled 0603

capacitors close the drain of the

high-side FET and connect with

vias to the GND plane on layer 2

Locate the output capacitors

(1210 footprint) close to the

inductor

Optional RC sense network for

inductor DCR current sensing

Shunt resistor for current sensing

with centrally placed sense vias

High-frequency switching current loop

with reduced effective area for lowest

power-loop parasitic inductance

Use large copper area for

heatsinking of the high-side FET

VIN

VOUT

PGND

Output capacitors (1210)

Shunt (1225)

Low-side

FET

6mm)

High-side

FET

6mm)

Inductor

Input

capacitors

(0603)

Input capacitors

(1210)

Keep the switch-node copper

area as small as possible

Place a pair of 1210 input capacitors

(C35, C37) on each side of the FET in

a butterfly layout for field cancellation

Place the inductor close to the FETs and

use a cutout of the copper underneath to

avoid parasitic coupling paths

Figure 8-31. Power Stage Component Layout

High-side

MOSFET

0603 input

capacitors

VIN

GND

0.3mm

vias

Tightly-coupled return path

minimizes power-loop impedance

0.15mm

Low-side

MOSFET

See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout application brief for more

detail.

Figure 8-32. PCB Stack-Up Diagram With Low L1-L2 Intra-layer Spacing

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LM5145 Datasheet(PDF) 60 Page - Texas Instruments

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