Data Sheet

LT83201

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Rev. A 35 of 45

Without fast start-up enabled, the RCtime constant, formed by the SET pin resistor and capacitor, controls soft-start

time. Connect the PGFB pin to INTVCC or to 0.5V to disable fast start-up. The ramp-up rate from 0% to 90% of nominal

VOUT is given by Equation 11.

tSTART_NO_FAST_START−UP = 2.3 × RSET × CSET

(11)

With fast-start-up enabled, the start-up time can be significantly reduced, with the ramp-up time from 0% to 90% of

the nominal VOUT given by Equation 12. For how the 2.7mA fast start-up current varies with temperature and VIN – VSET

differential voltage, see the Typical Performance Characteristics section.

tSTART_FAST_START−UP =

100μA × RSET × CSET

2.7mA

(12)

In most applications, fast start-up is enabled, in which case a minimum SET capacitor size of 1μF is recommended

for preventing reference voltage overcharge as well as ensuring good noise performance.

The SET pin is pulled to ground with a 520Ω MOSFET (RSET-PULLDOWN) during shutdown, thermal shutdown, VCC UVLO or

VIN UVLO. To ensure soft-start when the part exits any of the above conditions, there must have been sufficient time

to allow the SET pin to be pulled to close to ground prior to start-up. This time will be a function of the chosen SET

pin capacitance and RSET-PULLDOWN.

Fast Start-Up

For ultra-low noise applications that require low 1/f noise (that is, at frequencies below 100Hz), a larger value SET

pin capacitor is required, up to 22μF. A larger value capacitor can be used, but care should be taken regarding

leakage. While normally larger capacitors significantly increase the regulator’s start-up time, the LT83201

incorporates fast start-up circuitry that increases the SET pin current to about 2.7mA during start-up.

Upon start-up, the 2.7mA current source remains engaged while PGFB is below the power good start-up threshold

(VPGL_STARTUP) of 486.5mV, unless the regulator is in thermal shutdown, VIN is too low, or INTVCC has fallen too low.

The fast start-up circuit is permanently disabled once PGFB rises above VPGL_STARTUP until either the part is powered

down, or the part is placed into shutdown by pulling the EN/UVLO pin below 0.75V.

There is one more condition under which the 2.7mA current source is disabled during start-up. The purpose of this is

to prevent overcharging VSET. Since the part assumes that the PGFB pin is an accurate indication of the voltage on the

SET pin, it assumes that VOUTS follows VSET closely. However, this may not always be the case; for example, if the output

capacitance is very large or if, for some reason, the output is temporarily shorted to the GND. Therefore, fast charge

is disabled whenever VOUTS is lagging VSET by more than 30mV. This prevents incorrect behavior where the 2.7mA

current source stays on even when VSET has risen above its intended final value.

If programmable power good and fast start-up capabilities are not required, the PGFB pin must be connected to

either INTVCC or to 0.5V.

Programmable Power Good

As shown in the Block Diagram, the power good threshold is user programmable using the ratio of two external

resistors, RPGFB(BOT) and RPGFB(TOP) (see Equation 13).

VOUT(PG_THRESHOLD) = 0.5V × (1 +

RPGFB(TOP)

RPGFB(BOT)

) + IPGFB × RPGFB(TOP)

(13)

If the PGFB pin increases above 537.5mV or decreases below 462.5mV, the open-drain PG pin asserts and becomes

low impedance, indicating power is bad. The power good comparator has hysteresis of 10mV. The PGFB pin current