LT3045 datasheet(8/45 Pages) AD

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Data Sheet

LT83201

analog.com

Rev. A 8 of 45

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

LFCSP PACKAGE

15-Lead (3mm × 2mm × 0.75mm)

JEDEC BOARD JA = 50°C/W, JC(TOP) = 67.1°C/W, JC(PAD) = 10.4°C/W

DEMO BOARD JA = 33°C/W, ΨJT = 1.7°C/W

EXPOSED PAD IS GND AND SHOULD BE SOLDERED TO PCB

Figure 3. Pin Configurations

Table 3. Pin Descriptions

NAME

DESCRIPTION

A resistor is connected between the RT pin and ground to set the switching frequency.

The PG pin is the open-drain output of an internal comparator. PG pulls low until the

PGFB pin is within ±7.5% of 0.5V, and there are no fault conditions. PG is also pulled

low when EN/UVLO is below 0.75V, INTVCC has fallen too low or during thermal

shutdown. PG is valid when VIN is above 2.8V.

SYNC/MODE

For the LT83201, this pin programs three different operating modes: 1) Discontinuous

Conduction Mode: Connect this pin to GND for Discontinuous Conduction Mode (DCM)

to allow the part to operate in discontinuous mode at light loads for improved

efficiency. In this mode, the part may skip pulses at very light loads or very high duty

cycles to maintain regulation. 2) Forced Continuous Mode (FCM): This mode offers fast

transient response and full frequency operation over a wide load range. Connect this

pin high to INTVCC (~3.4V) or an external supply >1.5V for FCM. The part also operates in

this mode by default if this pin is left floating. 3) Synchronization Mode: Drive this pin

with a clock source to synchronize to an external frequency. During synchronization,

the part operates in forced continuous mode. Contact the factory for versions of this

part that replaces the SYNC/MODE pin with a CLKOUT pin. The CLKOUT pin would

provide a 50% duty-cycle square wave of the switching frequency, 180° out-of-phase

with the internal clock of the part, with a peak-to-peak amplitude of INTVCC to GND.

4, 8

VIN

The VIN pins supply current to the LT83201 internal circuitry and to the internal top-

side power switch. Two 0402 capacitors of 0.1µF or more should be placed to bypass

both VIN pins with positive terminal of input capacitor as close as possible to the VIN

pins, and the negative capacitor terminal as close as possible to the GND pins. VIN pins

must also be connected with an additional local bypass capacitor of 4.7µF or more. To

provide sufficient headroom for the current reference, VIN must be at least 700mV

higher than the required regulation setpoint that is programmed via the SET pin. For

example, for the required regulation setpoint of 3.3V, VIN must be at least 3.3V + 700mV

= 4V, or higher.

SYNC/MODE

VIN

BST

10 INTVCC

11 EN/UVLO

LT83201

TOP VIEW

16 GND

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