LT3045 datasheet(9/45 Pages) AD

9 / 45 page

Data Sheet

LT83201

analog.com

Rev. A 9 of 45

5, 7,

Exposed

Pad

GND

Ground. Place the negative terminal of the input capacitor as close to the GND pins as

possible. The exposed pads should be soldered to the PCB for good thermal

performance. If necessary due to manufacturing limitations, the exposed pad may be

left disconnected; however, the performance degrades.

The SW pin is the output of the internal power switches. Connect this pin to the

inductor. This node must be kept small on the PCB for good performance and low EMI.

BST

This pin is used to provide a drive voltage higher than the input voltage to the topside

power switch. Place a 0.1µF boost capacitor as close as possible to the IC.

INTVCC

Internal 3.4V Regulator Bypass Pin. The internal power drivers and control circuits are

current is supplied by VIN. Decouple this pin to ground with at least 1µF low equivalent

series resistance (ESR) ceramic capacitor placed close to the IC.

EN/UVLO

A voltage at this pin greater than 0.75V enables switching, and a voltage less than

200mV is guaranteed to shut down the internal current bias and sub-regulators. The

hysteretic threshold voltage is 0.75V going up and 0.7V going down. Connect to VIN if

the shutdown feature is not used. An external resistor divider from VIN is used to

program a VIN threshold below which the LT83201 shuts down.

The VC pin is the output of the internal error amplifier. The voltage on this pin controls

the peak switch current. Connect an RC network from this pin to ground to

compensate the control loop.

SET

This pin is the non-inverting input of the error amplifier and the regulation setpoint for

the LT83201. SET sources a precision 100μA current that flows through an external

resistor connected between the SET and GND. The LT83201’s output voltage is

determined by VSET = ISET × RSET when used in the default unity-gain configuration. The

SET pin voltage range is from 0V to 13V. For applications with output voltages above

13V, see the Output Voltages Above 13V section. A capacitor should be added from SET

to GND for the best noise performance. Increasing this capacitance further improves

noise at the expense of increased start-up time. See the Set Pin Capacitor: Noise and

Soft-Start section for important information on how to select this capacitor. For

optimum load regulation, Kelvin connect the ground side of the SET pin resistor

directly to the load. This pin is pulled to ground with a 520Ω MOSFET (RSET-PULLDOWN)

during shutdown and fault conditions.

OUTS

Output Sense. This pin is the inverting input to the error amplifier. For optimal

transient performance and load regulation, Kelvin connect OUTS directly to the output

capacitor and the load.

PGFB

Power Good Feedback. The PG pin pulls low if PGFB increases above 537.5mV or

decreases below 462.5mV. Connecting an external resistor divider between VOUT, PGFB,

and GND sets the programmable power good threshold with the following transfer

function: 0.5V (±7.5%) × (1 + RPGFB(TOP)/RPGFB(BOT)). As discussed in the Applications

Information section, PGFB also activates the fast start-up circuitry. The PGFB pin must

be connected to INTVCC or 0.5V if power good and fast start-up functionalities are not

needed.

LT3045 Datasheet(PDF) 9 Page - Analog Devices

LT3045 Datasheet(HTML) 9 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL