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TUSB322I Datasheet(PDF) 6 Page - Texas Instruments |
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TUSB322I Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 37 page  over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Rp_ODext External pullup resistor on open drain IOs (INT_N/OUT3, ID) 200 kΩ Rp_TLext Tri-level input external pullup resistor (ADDR) 4.7 kΩ I2C - SDA/OUT1, SCL/OUT2 can operate from 1.8 or 3.3 V (±10%) when ADDR pin is low or high. (2) VDD_I2C Supply range for I2C (SDA/OUT1, SCL/OUT2) 1.65 1.8 3.6 V VIH High-level signal voltage 1.05 V VIL Low-level signal voltage 0.4 V VOL Low-level signal output voltage (open drain) IOL = –1.6 mA 0.4 V VBUS_DET IO Pins (Connected to System VBUS signal) VBUS_THR VBUS threshold range 2.95 3.3 3.8 V RVBUS External resistor between VBUS and VBUS_DET pin 855 887 920 KΩ RVBUS_PD Internal pulldown resistance for VBUS_DET 95 KΩ DIR pin (Open Drain IO) VOL Low-level signal output voltage IOL = –1.6 mA 0.4 V VCONN RON On resistance of the VCONN power FET 1.25 Ω VTOL Voltage tolerance on VCONN power FET 5.5 V VPASS Voltage to pass through VCONN power FET 5.5 V IVCONN VCONN current limit; VCONN is disconnected above the value 225 300 375 mA CBULK Bulk capacitance on VCONN; placed on VDD supply 10 200 uF (1) VDD must be 3.5 V or greater to advertise 3 A current. (2) When using 3.3 V for I2C, customer must ensure VDD is above 3.0 V at all times. 5.6 Timing Requirements MIN NOM MAX UNIT I2C (SDA, SCL) tSU:DAT Data setup time 100 ns tHD;DAT Data hold time 10 ns tSU:STA Set-up time, SCL to start condition 0.6 µs tHD:STA Hold time, (repeated) start condition to SCL 0.6 µs tSU:STO Set up time for stop condition 0.6 µs tVD;DAT Data valid time 0.9 µs tVD;ACK Data valid acknowledge time 0.9 µs tBUF Bus free time between a stop and start condition 1.3 µs fSCL SCL clock frequency; I2C mode for local I2C control 400 kHz tr Rise time of both SDA and SCL signals 300 ns tf Fall time of both SDA and SCL signals 300 ns CBUS_100KHZ Total capacitive load for each bus line when operating at ≤ 100 KHz 400 pF CBUS_400KHZ Total capacitive load for each bus line when operating at 400 KHz. 100 pF TUSB322I SLLSEO5D – OCTOBER 2015 – REVISED MARCH 2021 www.ti.com 6 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TUSB322I |
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