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ADV7182

Data Sheet

CTA[2:0], Chroma Timing Adjust, Address 0x27[5:3]

The chroma timing adjust register allows the user to specify a

timing difference between chroma and luma samples. This can

be used to compensate for external filter group delay differences

in the luma vs. chroma path and to allow a different number of

pipeline delays while processing the video downstream. Review

this functionality together with the LTA[1:0] bits.

The chroma can be delayed or advanced only in chroma pixel

steps. One chroma pixel step is equal to two luma pixels. The

programmable delay occurs after demodulation, where delay

cannot be made by luma pixel steps.

For manual programming, use the following defaults:

•

CVBS input CTA[2:0] = 011

•

Y/C input CTA[2:0] = 101

•

YPrPb input CTA[2:0] = 110

Table 71. CTA Function

CTA[2:0]

Description

000

Reserved

001

Chroma + two pixels (early)

010

Chroma + one pixel (early)

011 (default)

No delay

100

Chroma − one pixel (late)

101

Chroma − two pixels (late)

110

Chroma − three pixels (late)

111

Reserved

SYNCHRONIZATION OUTPUT SIGNALS

HSYNC Configuration

The following controls allow the user to configure the behavior

of the HSYNC output signal only:

•

Beginning of HSYNC signal via HSB[10:0]

•

End of HSYNC signal via HSE[10:0]

•

Polarity of HSYNC using PHS

The HSYNC signal can be output on the VS/FIELD/SFL pin or

the HS pin (see the Global Pin Control section.)

The HSYNC begin (HSB) and HSYNC end (HSE) registers allow

the user to freely position the HSYNC signal within the video

line. The values in HSB[10:0] and HSE[10:0] are measured in

pixel units from the falling edge of HSYNC. Using both values,

the user can program both the position and length of the HSYNC

output signal.

HSB[10:0], HSYNC Begin, Address 0x34[6:4],

Address 0x35[7:0]

The position of this edge is controlled by placing a binary

number into HSB[10:0]. The number applied offsets the edge

with respect to an internal counter that is reset to 0 immediately

after EAV Code FF, 00, 00, XY (see Figure 31). HSB is set to

00000000010b, which is two LLC clock cycles from count [0].

The default value of HSB[10:0] is 0x02, indicating that the

HSYNC pulse starts two pixels after the falling edge of HSYNC.

HSE[10:0], HSYNC End, Address 0x34[2:0], Address 0x36[7:0]

The position of this edge is controlled by placing a binary

number into HSE[10:0]. The number applied offsets the edge

with respect to an internal counter that is reset to 0 immediately

after EAV Code FF, 00, 00, XY (see Figure 31). HSE is set to

00000000000b, which is 0 LLC clock cycles from count [0].

The default value of HSE[10:0] is 00, indicating that the HSYNC

pulse ends 0 pixels after the falling edge of HSYNC.

For example,

•

To shift the HSYNC toward active video by 20 LLCs, add

20 LLCs to both HSB and HSE, that is, HSB[10:0] =

[00000010110], HSE[10:0] = [00000010100].

•

To shift the HSYNC away from active video by 20 LLCs,

add 1696 LLCs to both HSB and HSE (for NTSC), that is,

HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].

Therefore, 1696 is derived from the NTSC total number of

pixels, 1716.

•

To move 20 LLCs away from active video, subtract 20 from

1716 and add the result in binary to both HSB[10:0] and

HSE[10:0].

PHS, HSYNC Polarity, Address 0x37[7]

The polarity of the HSYNC signal can be inverted using the

PHS bit.

When PHS is 0 (default), HSYNC is active low.

When PHS is 1, HSYNC is active high.

Table 72. HS Timing Parameters

Standard

Characteristic

HS Begin Adjust,

HSB[10:0] (Default)

HS End Adjust,

HSE[10:0] (Default)

HS to Active Video,

LLC Clock Cycles, C

in Figure 31 (Default)

Active Video Samples/

Line, D in Figure 31

Total LLC Clock

Cycles, E in Figure 31

NTSC

00000000010b

00000000000b

272

720Y + 720C = 1440

1716

PAL

00000000010b

00000000000b

284

720Y + 720C = 1440

1728

Figure 31. HSYNC Timing

ACTIVE

VIDEO

LLC

PIXEL

BUS

4 LLC

HSB[10:0]

HSE[10:0]

SAV

ACTIVE VIDEO

H BLANK

EAV

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Rev. C

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