ADV7182 datasheet(11/96 Pages) AD

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Data Sheet

ADV7182

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 4. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

1, 4

DGND

Ground for Digital Supply.

DVDDIO

Digital I/O Supply Voltage (1.8 V to 3.3 V).

3, 13

DVDD

Digital Supply Voltage (1.8 V).

5 to 12

P7 to P0

Video Pixel Output Port.

XTALP

This pin should be connected to the 28.6363 MHz crystal or not connected if an external

1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7182. In crystal mode, the

crystal must be a fundamental crystal.

XTALN

Input Pin for the 28.6363 MHz Crystal. This pin can be overdriven by an external 1.8 V,

28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.

PVDD

PLL Supply Voltage (1.8 V).

17, 18, 22, 23

AIN1 to AIN4

Analog Video Input Channels.

VREFP

Internal Voltage Reference Output.

VREFN

Internal Voltage Reference Output.

AVDD

Analog Supply Voltage (1.8 V).

INTRQ

Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video.

RESET

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7182 circuitry.

ALSB

This pin selects the I2C address for the ADV7182. For ALSB set to Logic 0, the address

selected for a write is 0x40; for ALSB set to Logic 1, the address selected is 0x42.

SDATA

I/O

I2C Port Serial Data Input/Output Pin.

SCLK

I2C Port Serial Clock Input. The maximum clock rate is 400 kHz.

VS/FIELD/SFL

Vertical Synchronization Output Signal/Field Synchronization Output Signal/Subcarrier

Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier

frequency when this decoder is connected to any Analog Devices digital video encoder.

Horizontal Synchronization Output Signal.

PWRDWN

A logic low on this pin places the ADV7182 is in power-down mode.

LLC

Line-Locked Output Clock for Output Pixel Data. Nominally 27 MHz but varies up or down

according to the video line length.

EPAD (EP)

The exposed pad must be connected to DGND.

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO DGND.

24 INTRQ

23 AIN4

22 AIN3

21 AVDD

20 VREFN

19 VREFP

18 AIN2

17 AIN1

DGND

DVDDIO

DVDD

DGND

ADV7182

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