AD9785-EBZ datasheet(22/64 Pages) AD

22 / 64 page

AD9785/AD9787/AD9788

Rev. 0 | Page 22 of 64

There are two phases to a communication cycle with the

AD9785/AD9787/AD9788. Phase 1 is the instruction cycle,

which is the writing of an instruction byte into the AD9785/

AD9787/AD9788, coincident with the first eight SCLK rising

edges. The instruction byte provides the AD9785/AD9787/

AD9788 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication

cycle. The instruction byte defines whether the upcoming data

transfer is read or write and the serial address of the register

being accessed.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9785/AD9787/

AD9788. The remaining SCLK edges are for Phase 2 of the

communication cycle. Phase 2 is the actual data transfer

between the AD9785/AD9787/AD9788 and the system

controller. The number of bytes transferred during Phase 2 of

the communication cycle is a function of the register being

accessed.

For example, when accessing the frequency tuning word (FTW)

bytes be transferred. If accessing the amplitude scale factor (ASF)

bytes be transferred. After transferring all data bytes per the

instruction byte, the communication cycle is completed.

At the completion of any communication cycle, the AD9785/

AD9787/AD9788 serial port controller expects the next eight

rising SCLK edges to be the instruction byte of the next

communication cycle.

All data input is registered on the rising edge of SCLK. All data

is driven out of the AD9785/AD9787/AD9788 on the falling

edge of SCLK.

Figure 43 through Figure 46 are useful in understanding the

general operation of the AD9785/AD9787/AD9788 serial port.

R/W N1 N0

A4 A3

A2 A1 A0 D7 D6N D5N

D00

D10

D20

D30

D7 D6N D5N

D00

D10

D20

D30

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SPI_CSB

SCLK

SPI_SDIO

SPI_SDO

Figure 43. Serial Register Interface Timing, MSB First

A0 A1 A2

A3 A4

N0 N1 R/W D00 D10 D20

D7N

D6N

D5N

D4N

D00 D10 D20

D7N

D6N

D5N

D4N

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SPI_CSB

SCLK

SPI_SDIO

SPI_SDO

Figure 44. Serial Register Interface Timing, LSB First

INSTRUCTION BIT 6

INSTRUCTION BIT 7

SPI_CSB

SCLK

SPI_SDIO

tDS

tDH

tPWH

tPWL

tSCLK

Figure 45. SPI Register Write Timing

DATA BIT n–1

DATA BIT n

SPI_CSB

SCLK

SPI_SDIO

SPI_SDO

tDV

Figure 46. SPI Register Read Timing Instruction Byte

AD9785-EBZ Datasheet(PDF) 22 Page - Analog Devices

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