AD9785-EBZ datasheet(30/64 Pages) AD

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AD9785/AD9787/AD9788

Rev. 0 | Page 30 of 64

The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the

digital logic. No digital functionality within the main digital block is required.

Table 16. Auxiliary DAC 1 Control Register

Address

Bit

Name

Description

0: Default. If the Auxiliary DAC 1 sign bit is cleared, the Aux DAC 1 sign is positive.

Pin 90 is the active pin.

[15]

Auxiliary DAC 1 sign

1: If the Auxiliary DAC 1 sign bit is set, the Aux DAC 1 sign is negative. Pin 89 is the

active pin.

0: Default. If the Auxiliary DAC 1 current direction bit is cleared, the Aux DAC 1 sources

current.

[14]

Auxiliary DAC 1

current direction

1: If the Auxiliary DAC 1 current direction bit is set, the Aux DAC 1 sinks current.

0: Default. If the Auxiliary DAC 1 power-down bit is cleared, the Aux DAC 1 is active.

[13]

Auxiliary DAC 1

power-down

1: If the Auxiliary DAC 1 power-down bit is set, the Aux DAC 1 is inactive and enters a

low power state.

[12:10]

Reserved

Reserved for future use.

0x06

[9:0]

Auxiliary DAC 1 data

These bits are the Auxiliary DAC 1 gain adjustment bits.

The Q DAC control register comprises two bytes located at Address 0x07. These bits are routed directly to the periphery of the digital

logic. No digital functionality within the main digital block is required.

Table 17. Q DAC Control Register

Address

Bit

Name

Description

0: Default. If the Q DAC sleep bit is cleared, the Q DAC is active.

[15]

Q DAC sleep

1: If the Q DAC sleep bit is set, the Q DAC is inactive and enters a low power state.

0: Default. If the Q DAC power-down bit is cleared, the Q DAC is active.

[14]

Q DAC power-down

1: If the Q DAC power-down bit is set, the Q DAC is inactive and enters a low power state.

[13:10]

Reserved

Reserved for future use.

0x07

[9:0]

Q DAC gain adjustment

These bits are the Q DAC gain adjustment bits.

The Auxiliary DAC 2 control register comprises two bytes located at Address 0x08. These bits are routed directly to the periphery of the

digital logic. No digital functionality within the main digital block is required.

Table 18. Auxiliary DAC 2 Control Register

Address

Bit

Name

Description

0: Default. If the Auxiliary DAC 2 sign bit is cleared, the Aux DAC 2 sign is positive.

Pin 86 is the active pin.

[15]

Auxiliary DAC 2 sign

1: If the Auxiliary DAC 2 sign bit is set, the Aux DAC 2 sign is negative. Pin 87 is the

active pin.

0: Default. If the Auxiliary DAC 2 current direction bit is cleared, the Aux DAC 2 sources

current.

[14]

Auxiliary DAC 2

current direction

1: If the Auxiliary DAC 2 current direction bit is set, the Aux DAC 2 sinks current.

0: Default. If the Auxiliary DAC 2 power-down bit is cleared, the Aux DAC 2 is active.

[13]

Auxiliary DAC 2

power-down

1: If the Auxiliary DAC 2 power-down bit is set, the Aux DAC 2 is inactive and enters

a low power state.

[12:10]

Reserved

Reserved for future use.

0x08

[9:0]

Auxiliary DAC 2 data

These bits are the Auxiliary DAC 2 gain adjustment bits.

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