PVDD to PGND.......................................................-0.3V to +30V

AGND to PGND.....................................................-0.3V to +0.3V

INL, INR, FBL, FBR, COM to AGND........-0.3V to (VREG + 0.3V)

MUTE, SHDN, MONO, MOD, REGEN to AGND.......-0.3V to +6V

REG to AGND..............................................-0.3V to (VS + 0.3V)

VS to AGND (Note 1)................................................-0.3V to +6V

OUTL+, OUTL-, OUTR+,

OUTR-, to PGND................................-0.3V to (PVDD + 0.3V)

C1N to PGND..........................................-0.3V to (PVDD + 0.3V)

C1P to PGND..........................(PVDD - 0.3V) to (VBOOT + 0.3V)

BOOT to PGND.............................(VC1P - 0.3V) to PVDD + 12V

OUTL+, OUTL-, OUTR+, OUTR-,

Short Circuit to PGND or PVDD.............................Continuous

Thermal Limits (Notes 2, 3)

Continuous Power Dissipation (TA = +70°C)

32-Pin TQFN 5mm x 5mm Multiple Layer PCB

(derate 34.5mW/°C above +70°C).................................2.76W

θJA................................................................................29°C/W

θJC..................................................................................2°C/W

Continuous Power Dissipation (TA = +70°C)

32-Pin TQFN 7mm x 7mm Multiple Layer PCB

(derate 37mW/°C above +70°C)....................................2.96W

θJA................................................................................27°C/W

θJC..................................................................................1°C/W

Operating Temperature Range.............................-40°C to +85°C

Storage Temperature Range..............................-65°C to +150°C

Junction Temperature.......................................................+150°C

Lead Temperature (soldering, 10s)...................................+300°C

32 TQFN-EP (7mm x 7mm)

Package Code

T3277-3

Outline Number

21-0144

32 TQFN-EP (5mm x 5mm)

Package Code

T3255-4

Outline Number

21-0140

Package Information

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.

For detailed information on package thermal considerations, refer to

www.maximintegrated.com/thermal-tutorial.

For the latest package outline information and land patterns (footprints), go to

www.maximintegrated.com/packages. Note that a “+”,

“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing

pertains to the package regardless of RoHS status.

MAX9736

Mono/Stereo High-Power Class D Amplifier

www.maximintegrated.com

Maxim Integrated │ 2

Note 1: VS cannot exceed PVDD + 0.3V. See the Power-Supply Sequencing section.

Note 2: Thermal performance of this device is highly dependant on PCB layout. See the Applications Information section for more details.

Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to

www.maximintegrated.com/thermal-tutorial.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.