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C8051F310 Datasheet(PDF) 147 Page - Silicon Laboratories |
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C8051F310 Datasheet(HTML) 147 Page - Silicon Laboratories |
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147 / 228 page ![]() Rev. 1.7 147 C8051F310/1/2/3/4/5/6/7 The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation. All transactions are initiated by a master, with one or more addressed slave devices as the target. The master generates the START condition and then transmits the slave address and direction bit. If the trans- action is a WRITE operation from the master to the slave, the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte. For READ operations, the slave transmits the data waiting for an ACK from the master at the end of each byte. At the end of the data transfer, the master generates a STOP condition to terminate the transaction and free the bus. Figure 14.3 illustrates a typical SMBus transaction. Figure 14.3. SMBus Transaction 14.3.1. Arbitration A master may start a transfer only if the bus is free. The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time (see Section “14.3.4. SCL High (SMBus Free) Timeout” on page 148). In the event that two or more devices attempt to begin a transfer at the same time, an arbi- tration scheme is employed to force one master to give up the bus. The master devices continue transmit- ting until one attempts a HIGH while the other transmits a LOW. Since the bus is open-drain, the bus will be pulled LOW. The master attempting the HIGH will detect a LOW SDA and lose the arbitration. The win- ning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. This arbitration scheme is non-destructive: one device always wins, and no data is lost. SLA6 SDA SLA5-0 R/W D7 D6-0 SCL Slave Address + R/W Data Byte START ACK NACK STOP |
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