C8051F310 datasheet(148/228 Pages) SILABS

148 / 228 page

C8051F310/1/2/3/4/5/6/7

148

Rev. 1.7

14.3.2. Clock Low Extension

SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different

speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow

slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line

LOW to extend the clock low period, effectively decreasing the serial clock frequency.

14.3.3. SCL Low Timeout

If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,

the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus

protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than

25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-

cation no later than 10 ms after detecting the timeout condition.

When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to

reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to

overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable

and re-enable) the SMBus in the event of an SCL low timeout.

14.3.4. SCL High (SMBus Free) Timeout

The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus

is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and

SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a

Master START, the START will be generated following this timeout. Note that a clock source is required for

free timeout detection, even in a slave-only implementation.

C8051F310 Datasheet(PDF) 148 Page - Silicon Laboratories