C8051F310 datasheet(173/228 Pages) SILABS

173 / 228 page

Rev. 1.7

173

C8051F310/1/2/3/4/5/6/7

16. Enhanced Serial Peripheral Interface (SPI0)

The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous

serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-

tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input

to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding

contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can

also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-

eral purpose port I/O pins can be used to select multiple slave devices in master mode.

Figure 16.1. SPI Block Diagram

SFR Bus

Data Path

Control

SFR Bus

Write

SPI0DAT

Receive Data Buffer

SPI0DAT

Shift Register

SPI CONTROL LOGIC

SPI0CKR

SPI0CFG

SPI0CN

Pin Interface

Control

Logic

Port I/O

Read

SPI0DAT

SPI IRQ

Tx Data

Rx Data

SCK

MOSI

MISO

NSS

Transmit Data Buffer

Clock Divide

Logic

SYSCLK

C8051F310 Datasheet(PDF) 173 Page - Silicon Laboratories

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