C8051F310 datasheet(178/228 Pages) SILABS

178 / 228 page

C8051F310/1/2/3/4/5/6/7

178

Rev. 1.7

16.5. Serial Clock Timing

Four combinations of serial clock phase and polarity can be selected using the clock control bits in the

SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases

(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low

clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0

should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The

clock and data line relationships for master mode are shown in Figure 16.5. For slave mode, the clock and

data relationships are shown in Figure 16.6 and Figure 16.7. CKPHA must be set to ‘0’ on both the master

and slave SPI when communicating between two of the following devices: C8051F04x, C8051F06x,

C8051F12x, C8051F31x, C8051F32x, and C8051F33x

The SPI0 Clock Rate Register (SPI0CKR) as shown in SFR Definition 16.3 controls the master mode

serial clock frequency. This register is ignored when operating in slave mode. When the SPI is configured

as a master, the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz,

whichever is slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for

full-duplex operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-

wire slave mode), and the serial input data synchronously with the slave’s system clock. If the master

issues SCK, NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec)

must be less than 1/10 the system clock frequency. In the special case where the master only wants to

transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the

SPI slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency.

This is provided that the master issues SCK, NSS, and the serial input data synchronously with the slave’s

system clock.

Figure 16.5. Master Mode Data/Clock Timing

SCK

(CKPOL=0, CKPHA=0)

SCK

(CKPOL=0, CKPHA=1)

SCK

(CKPOL=1, CKPHA=0)

SCK

(CKPOL=1, CKPHA=1)

MSB

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MISO/MOSI

NSS (Must Remain High

in Multi-Master Mode)

C8051F310 Datasheet(PDF) 178 Page - Silicon Laboratories

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