C8051F310 datasheet(180/228 Pages) SILABS

180 / 228 page

C8051F310/1/2/3/4/5/6/7

180

Rev. 1.7

16.6. SPI Special Function Registers

SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN

Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate

following register definitions.

SFR Definition 16.1. SPI0CFG: SPI0 Configuration

Bit 7:

SPIBSY: SPI Busy (read only).

This bit is set to logic 1 when a SPI transfer is in progress (Master or slave Mode).

Bit 6:

MSTEN: Master Mode Enable.

0: Disable master mode. Operate in slave mode.

1: Enable master mode. Operate as a master.

Bit 5:

CKPHA: SPI0 Clock Phase.

This bit controls the SPI0 clock phase.

0: Data centered on first edge of SCK period.*

1: Data centered on second edge of SCK period.*

Bit 4:

CKPOL: SPI0 Clock Polarity.

This bit controls the SPI0 clock polarity.

0: SCK line low in idle state.

1: SCK line high in idle state.

Bit 3:

SLVSEL: Slave Selected Flag (read only).

This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected slave. It

is cleared to logic 0 when NSS is high (slave not selected). This bit does not indicate the

instantaneous value at the NSS pin, but rather a de-glitched version of the pin input.

Bit 2:

NSSIN: NSS Instantaneous Pin Input (read only).

This bit mimics the instantaneous value that is present on the NSS port pin at the time that

the register is read. This input is not de-glitched.

Bit 1:

SRMT: Shift Register Empty (Valid in Slave Mode, read only).

This bit will be set to logic 1 when all data has been transferred in/out of the shift register,

and there is no new information available to read from the transmit buffer or write to the

receive buffer. It returns to logic 0 when a data byte is transferred to the shift register from

the transmit buffer or by a transition on SCK.

NOTE: SRMT = 1 when in Master Mode.

Bit 0:

RXBMT: Receive Buffer Empty (Valid in Slave Mode, read only).

This bit will be set to logic 1 when the receive buffer has been read and contains no new

information. If there is new information available in the receive buffer that has not been read,

this bit will return to logic 0.

NOTE: RXBMT = 1 when in Master Mode.

*Note:

In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is

sampled one SYSCLK before the end of each data bit, to provide maximum settling time for the slave

device. See Table 16.1 for timing parameters.

R/W

Reset Value

SPIBSY

MSTEN

CKPHA

CKPOL

SLVSEL

NSSIN

SRMT

RXBMT

00000111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address: 0xA1

C8051F310 Datasheet(PDF) 180 Page - Silicon Laboratories

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