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TMS320DM642 Datasheet(PDF) 64 Page - Texas Instruments |
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TMS320DM642 Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 176 page  www.ti.com TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200L – JULY 2002 – REVISED JANUARY 2007 Table 3-8. DM642 Device Multiplexed Pin Configurations(1) (continued) MULTIPLEXED PINS DEFAULT DEFAULT DESCRIPTION FUNCTION SETTING NAME NO. VP1D[8]/CLKR1 AD8 VP1D[7]/FSR1 AC7 By default, the McBSP1 peripheral, function is enabled VP1D[6]/DR1 AD7 VP1EN bit = 0 (disabled) upon reset (MCBSP1EN bit = 1). McBSP1 VP1D[5]/CLKS1 AE7 MCBSP1EN bit = 1 functions To enable the Video Port 1 data pins, the VP1EN bit in the (enabled) VP1D[4]/DX1 AC6 PERCFG register must be set to a 1. VP1D[3]/FSX1 AD6 VP1D[2]/CLKX1 AE6 VP0D[19]/AHCLKX0 AC12 VP0D[18]/AFSX0 AD12 By default, no function is enabled upon reset. VP0D[17]/ACLKX0 AB13 To enable the Video Port 0 data pins, the VP0EN bit in the VP0EN bit = 0 (disabled) PERCFG register must be set to a 1. (McASP0 control VP0D[16]/AMUTE0 AC13 None MCASP0EN bit = 0 pins are disabled). VP0D[15]/AMUTEIN0 AD13 (disabled) To enable the McASP0 control pins, the MCASP0EN bit in VP0D[14]/AHCLKR0 AB14 the PERCFG register must be set to a 1. (VP0 upper data VP0D[13]/AFSR0 AC14 pins are disabled). VP0D[12]/ACLKR0 AD14 VP0D[8]/CLKR0 AE15 VP0D[7]/FSR0 AB16 By default, the McBSP0 peripheral function is enabled VP0D[6]/DR0 AC16 VP0EN bit = 0 (disabled) upon reset (MCBSP0EN bit = 1). McBSP0 VP0D[5]/CLKS0 AD16 MCBSP0EN bit = 1 functions To enable the Video Port 0 data pins, the VP0EN bit in the (enabled) VP0D[4]/DX0 AE16 PERCFG register must be set to a 1. VP0D[3]/FSX0 AF16 VP0D[2]/CLKX0 AF17 XSP_CLK/MDCLK R5 By default, no functions enabled upon reset (PCI is disabled). To enable the PCI peripheral, an external pullup resistor PCI_EN = 0 (disabled)(1) (1 k Ω) must be provided on the PCI_EN pin (setting None MAC_EN = 0 PCI_EN = 1 at reset) XSP_DO/MDIO P5 (disabled)(1) To enable the MDIO peripheral (which also enables the EMAC peripheral), an external pullup resistor (1 k Ω) must be provided on the MAC_EN pin (setting MAC_EN = 1 at reset) HAS/PPAR P3 HAS HCNTL1/PDEVSEL P1 HCNTL1 HCNTL0/PSTOP R3 HCNTL0 HDS1/PSERR R2 HDS1 By default, HPI is enabled upon reset (PCI is disabled). HDS2/PCBE1 T2 HDS2 To enable the PCI peripheral, an external pullup resistor PCI_EN = 0 (disabled)(1) HR/W/PCBE2 M1 HR/W (1 k Ω) must be provided on the PCI_EN pin (setting HHWIL PCI_EN = 1 at reset). HHWIL/PTRDY N3 (HPI16 only) HINT/PFRAME N4 HINT HCS/PPERR R1 HCS HRDY/PIRDY N1 HRDY Device Configurations 64 Submit Documentation Feedback |
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