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TMS320DM642 Datasheet(PDF) 24 Page - Texas Instruments |
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TMS320DM642 Datasheet(HTML) 24 Page - Texas Instruments |
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24 / 176 page  www.ti.com McBSPs (Multichannel Buffered Serial Ports) VP0D[2]/CLKX0(A) VP0D[3]/FSX0(A) VP0D[4]/DX0(A) VP0D[8]/CLKR0(A) VP0D[7]/FSR0(A) VP0D[6]/DR0(A) VP0D[5]/CLKS0(A) McBSP0 VP1D[2]/CLKX1(A) VP1D[3]/FSX1(A) VP1D[4]/DX1(A) VP1D[8]/CLKR1(A) VP1D[7]/FSR1(A) VP1D[6]/DR1(A) VP1D[5]/CLKS1(A) McBSP1 TOUT0/MACEN Timers TINP0 TOUT1/LENDIAN Timer 1 TINP1 Timer 2 Timer 0 SCL0 I2C0 I2C0 SDA0 Transmit Receive Clock Transmit Receive Clock TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor SPRS200L – JULY 2002 – REVISED JANUARY 2007 A. These McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals, respectively. By default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins, see the Device Configurations section of this data sheet. Figure 2-10. McBSP/Timer/I2C0 Peripheral Signals Device Overview 24 Submit Documentation Feedback |
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