TMS320DM642 datasheet(84/176 Pages) TI

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5.5.2

Interrupts Peripheral Register Description(s)

5.5.3

External Interrupts Electrical Data/Timing

EXT_INTx, NMI

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Table 5-7. DM642 DSP Interrupts (continued)

INTERRUPT

CPU

SELECTOR

INTERRUPT

VALUE

INTERRUPT SOURCE

CONTROL

EVENT

NUMBER

(BINARY)

–

11100

AXINT0

McASP0 transmit interrupt

–

11101

ARINT0

McASP0 receive interrupt

–

11110 – 11111

Reserved

Reserved. Do not use.

Table 5-8. Interrupt Selector Registers (C64x)

HEX ADDRESS RANGE

ACRONYM

COMMENTS

Selects which interrupts drive CPU

019C 0000

MUXH

Interrupt multiplexer high

interrupts 10–15 (INT10–INT15)

Selects which interrupts drive CPU

019C 0004

MUXL

Interrupt multiplexer low

interrupts 4–9 (INT04–INT09)

Sets the polarity of the external

019C 0008

EXTPOL

External interrupt polarity

interrupts (EXT_INT4–EXT_INT7)

019C 000C – 019F FFFF

–

Reserved

Table 5-9. Timing Requirements for External Interrupts

(1) (see Figure 5-8)

–500

–600

NO.

UNIT

–720

MIN

MAX

Width of the NMI interrupt pulse low

tw(ILOW)

Width of the EXT_INT interrupt pulse low

Width of the NMI interrupt pulse high

tw(IHIGH)

Width of the EXT_INT interrupt pulse high

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

Figure 5-8. External/NMI Interrupt Timing

DM642 Peripheral Information and Electrical Specifications

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