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TMS320DM642 Datasheet(PDF) 87 Page - Texas Instruments

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Part # TMS320DM642
Description  Video/Imaging Fixed-Point Digital Signal Processor
PDF  176 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM642 Datasheet(HTML) 87 Page - Texas Instruments

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AECLKOUT2
17
14
1
CLKOUT4
CLKOUT6
RESET
AECLKIN
Boot and Device
Configuration Inputs (C)
16
15
3
2
10
8
11
9
7
6
13
12
AECLKOUT1
5
4
PCLK
18
Low Group (A)
Z Group (A)(B)
EMIF Z Group (A)(B)
EMIF High Group (A)
EMIF Low Group (A)
TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200L – JULY 2002 – REVISED JANUARY 2007
A.
EMIF
Z
group
consists
of:
AEA[22:3],
AED[63:0],
ACE[3:0],
ABE[7:0],
AARE/ASDCAS/ASADS/ASRE,
AAWE/ASDWE/ASWE,
AAOE/ASDRAS/ASOE,
ASOE3,
ASDCKE,
and
APDT
EMIF
high
group
consists
of:
AHOLDA
(when
the
corresponding
HOLD
input
is
high)
EMIF
low
group
consists
of:
ABUSREQ;
AHOLDA
(when
the
corresponding
HOLD
input
is
low)
Low group consists of: XSP_CS, XSP_CLK/MDCLK, and XSP_DO/MDIO all of which apply only when PCI
EEPROM is enabled (with PCI_EN = 1 and MCBSP2_EN = 0). Otherwise, the XSP_CLK/MDCLK and
XSP_DO/MDIO pins are in the Z group. For more details on the PCI configuration pins, see the Device Configurations
section
of
this
data
sheet.
Z group consists of: HD[31:0]/AD[31:0] and the muxed EMAC output pins, XSP_CLK/MDCLK, XSP_DO/MDIO,
VP0D[2]/CLKX0, VP1D[2]/CLKX1, VP0D[3]/FSX0, VP1D[3]/FSX1, VP0D[4]/DX0, VP1D[4]/DX1, VP0D[8]/CLKR0,
VP1D[8]/CLKR1, VP0D[7]/FSR0, VP1D[7]/FSR1, TOUT0, TOUT1, VDAC/GP0[8]/PCI66, GP0[7:0], GP0[10]/PCBE3,
HR/W/PCBE2,
HDS2/PCBE1,
PCBE0,
GP0[13]/PINTA,
GP0[11]/PREQ,
HDS1/PSERR,
HCS/PPERR,
HCNTL1/PDEVSEL, HAS/PPAR,
HCNTL0/PSTOP,
HHWIL/PTRDY
(16-bit
HPI
mode
only),
HRDY/PIRDY,
HINT/PFRAME, VP0D[19:9, 6,5,1,0], VP1D[19:9, 6,5,1,0], and VP2D[19:0].
B.
If AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5 pins are actively driven, care must be taken to ensure no timing
contention between parameters 6, 7, 14, 15, 16, and 17.
C.
Boot and Device Configurations Inputs (during reset) include: AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5.
The PCI_EN pin must be driven valid at all times and the user must not switch values throughout device operation.
Figure 5-9. Reset Timing(A)
Submit Documentation Feedback
DM642 Peripheral Information and Electrical Specifications
87



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