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5.6 Reset

5.6.1

Reset Electrical Data/Timing

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

A hardware reset (RESET) is required to place the DSP into a known good state out of power-up. The

RESET signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core

and I/O voltages have reached their proper operating conditions. As a best practice, reset should be held

low during power-up. Prior to deasserting RESET (low-to-high transition), the core and I/O voltages should

be at their proper operating conditions and CLKIN should also be running at the correct frequency. When

PCI is enabled, the PCI input clock (PCLK) must be running prior to deasserting RESET as well.

When the PCI peripheral is enabled, a WARMRESET can be performed via the host. A WARMRESET

performs the same functionality as a hardware reset, but does not relatch the boot configuration pins.

Whatever boot configuration that was latched on the previous hardware reset will be performed during the

WARMRESET.

A hardware reset does not reset the PCI peripheral state machine. The PCI state machine is reset via the

PRST signal. The PRST signal does not affect the DSP.

Emulation resets, done using Code Composer Studio™ IDE, have the same affect as a PCI

WARMRESET.

For information on peripheral selection at the rising edge of RESET, see the Device Configuration section

of this data manual.

Table 5-10. Timing Requirements for Reset (see Figure 5-9)

–500

–600

NO.

UNIT

–720

MIN

MAX

tw(RST)

Width of the RESET pulse

250

µs

tsu(boot)

Setup time, boot configuration bits valid before RESET high (1)

4E or 4C(2)

th(boot)

Hold time, boot configuration bits valid after RESET high (1)

4P(3)

tsu(PCLK-RSTH)

Setup time, PCLK active before RESET high(4)

32N

(1)

AEA[22:19], LENDIAN, PCIEEAI, and HD5/AD5 are the boot configuration pins during device reset.

(2)

E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns.

Select the MIN parameter value, whichever value is larger.

(3)

P = 1/CPU clock frequency in ns. For example, when running parts at 720 MHz, use P = 1.39 ns.

(4)

N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter must be met.

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DM642 Peripheral Information and Electrical Specifications

TMS320DM642 Datasheet(PDF) 85 Page - Texas Instruments

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