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TMS320DM642 Datasheet(PDF) 103 Page - Texas Instruments

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Part # TMS320DM642
Description  Video/Imaging Fixed-Point Digital Signal Processor
PDF  176 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320DM642 Datasheet(HTML) 103 Page - Texas Instruments

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AECLKOUTx
ACEx
ABE[7:0]
AEA[12:3]
AED[63:0]
AEA13
AAOE/ASDRAS/ASOE (A)
AARE/ASDCAS/ASADS/ASRE (A)
AAWE/ASDWE/ASWE(A)
AEA[22:14]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
APDT (B)
14
14
TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor
SPRS200L – JULY 2002 – REVISED JANUARY 2007
A.
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as ASDCAS, ASDWE,
and ASDRAS, respectively, during SDRAM accesses.
B.
APDT signal is only asserted when the EDMA is in PDT mode (set the PDTS bit to 1 in the EDMA options parameter
RAM). For APDT read, data is not latched into EMIF. The PDTRL field in the PDT control register (PDTCTL)
configures the latency of the APDT signal with respect to the data phase of a read transaction. The latency of the
APDT signal for a read can be programmed to 0, 1, 2, or 3 by setting PDTRL to 00, 01, 10, or 11, respectively.
PDTRL equals 00 (zero latency) in Figure 5-22.
Figure 5-22. SDRAM Read Command (CAS Latency 3) for EMIFA
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DM642 Peripheral Information and Electrical Specifications
103



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