32C8B datasheet(46/69 Pages) RENESAS

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M32C/8B Group

5. Electrical Characteristics

REJ03B0242-0050 Rev.0.50 Oct 31, 2008

Page 46 of 67

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

Switching Characteristics

(VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85

°C unless otherwise specified)

Table 5.27

Memory Expansion Mode and Microprocessor Mode (when accessing external

memory space)

NOTES:

1. Values, which depend on BCLK frequency, can be obtained from the following equations.

109

f(BCLK) × 2

- 10 [ns]

th(WR-DB) =

109

f(BCLK) × 2

- 10 [ns]

th(WR-AD) =

109

f(BCLK) × 2

- 10 [ns]

th(WR-CS) =

2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following

equations.

109 × n

f(BCLK) × 2

- 15 [ns] (if external bus cycle is a

φ + bφ, n = (b × 2) - 1)

tw(WR)

109 × m

f(BCLK)

- 20 [ns] (if external bus cycle is a

φ + bφ, m = b)

td(DB-WR)

3. tc [ns] is added when recovery cycle is inserted.

Symbol

Parameter

Measurement

Condition

Standard

Unit

Min.

Max.

td(BCLK-AD)

Address output delay time

See Figure 5.2

th(BCLK-AD)

Address output hold time (BCLK standard)

-3

th(RD-AD)

Address output hold time (RD standard)(3)

th(WR-AD)

Address output hold time (WR standard)(3)

(note 1)

td(BCLK-CS)

Chip-select signal output delay time

th(BCLK-CS)

Chip-select signal output hold time (BCLK standard)

-3

th(RD-CS)

Chip-select signal output hold time (RD standard)(3)

th(WR-CS)

Chip-select signal output hold time (WR standard)(3)

(note 1)

td(BCLK-RD)

RD signal output delay time

th(BCLK-RD)

RD signal output hold time

-5

td(BCLK-WR)

WR signal output delay time

th(BCLK-WR)

WR signal output hold time

-5

td(DB-WR)

Data output delay time (WR standard)

(note 2)

th(WR-DB)

Data output hold time (WR standard)(3)

(note 1)

tw(WR)

WR output width

(note 2)

VCC1 = VCC2 = 5V

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