32C8B datasheet(60/69 Pages) RENESAS

60 / 69 page

M32C/8B Group

5. Electrical Characteristics

REJ03B0242-0050 Rev.0.50 Oct 31, 2008

Page 60 of 67

Under development Preliminary specification

Specifications in this manual are tentative and subject to change.

Timing Requirements

(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85

°C unless otherwise specified)

Table 5.47

Memory Expansion Mode and Microprocessor Mode

NOTE:

1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following

equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.

109 × m

f(BCLK) × 2

- 35 [ns] (if external bus cycle is a

φ + bφ, m = (b × 2) + 1)

tac1(RD-DB) =

109 × n

f(BCLK)

- 35 [ns] (if external bus cycle is a

φ + bφ, n = a + b)

tac1(AD-DB) =

109 × m

f(BCLK) × 2

- 35 [ns] (if external bus cycle is a

φ + bφ, m = (b × 2) - 1)

tac2(RD-DB) =

109 × p

f(BCLK) × 2

- 35 [ns] (if external bus cycle is a

φ + bφ, p = {(a + b - 1) × 2} + 1)

tac2(AD-DB) =

Symbol

Parameter

Standard

Unit

Min.

Max.

tac1(RD-DB)

Data input access time (RD standard)

(note 1)

tac1(AD-DB)

Data input access time (AD standard, CS standard)

(note 1)

tac2(RD-DB)

Data input access time (RD standard, when accessing a space with the

multiplexed bus)

(note 1)

tac2(AD-DB)

Data input access time (AD standard, when accessing a space with the

multiplexed bus)

(note 1)

tsu(DB-BCLK)

Data input setup time

tsu(RDY-BCLK)

RDY input setup time

tsu(HOLD-BCLK) HOLD input setup time

th(RD-DB)

Data input hold time

th(BCLK-RDY)

RDY input hold time

th(BCLK-HOLD)

HOLD input hold time

td(BCLK-HLDA)

HLDA output delay time

VCC1 = VCC2 = 3.3 V

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